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ZL30226/7/8 4/8/16 Port IMA/TC PHY Device for xDSL
Data Sheet Features
IMA * * * * * Up to 16 xDSL links & up to 8 IMA groups with 1 to 16 links/IMA group1 Supports symmetrical & asymmetrical operation CTC (common transmit) & ITC (independent transmit) clocking modes Pre-processing of RX ICP (IMA control protocol) cells IMA layer & per link statistics and alarms for performance monitoring with MIB support * Ordering Information ZL30226/GA ZL30227/GA ZL30228/GA 384 Pin PBGA 384 Pin PBGA 384 Pin PBGA
March 2004
-40C to +85C HEC (header error control) verification & generation, error detection, filler cell filtering (IMA) and idle/unassigned cell filtering (TC) TC layer statistics and error counts i.e. HEC errors with MIB support
*
TC and UNI * Supports mixed-mode operation: links not assigned to an IMA group can be used in TC mode ATM framing using cell delineation Standards Compliant * * ATM Forum - IMA 1.1 (AF-PHY-0086.001) & backwards compatible with IMA 1.0 ITU G.804 cell mapping & ITU I.432 cell delineation
*
1. ZL30226 supports up to 4 serial links with maximum 4 groups to be used - groups 0, 1, 2, 3. ZL30227 supports up to 8 serial links ZL30228 supports up to 16 serial links
RX External Static RAM
TDM Ring
RX Utopia Level 2 BUS TX
Rx Utopia FIFo
Internal IMA Processors (1 per group)
TDM Ring Control S/P
xDSL
Utopia I/F CTRL
Cell Delineator CD Circuits (1 per link)
xDSL
P/S Tx Utopia FIFo
Transmission Convergence
TDM Ring Control
xDSL Serial TDM Ports (1 per link, up to 10Mb/s per link)
TC Circuits (1 per link) Processor I/F
TDM Ring
Figure 1 - ZL30226/7/8 Block Diagram with Built-in IMA functions for up to 8 IMA Groups over 4/8/16 links 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30226/7/8
General * * * * * * * * * * Supports TDM serial links up to 10 Mb/s for xDSL Single chip ATM IMA & TC processor Versatile TDM interface for most popular xDSL chipsets Up to 6 ZL30226/7/8 devices can be spanned using a TDM ring supporting 32 links
Data Sheet
Provides 8 & 16-bit UTOPIA Level 1 & 2 compatible MPHY Interface (ZL30226/7/8 slaved to ATM device) 16-bit microprocessor interface for Intel or Motorola JTAG test support 2.5 V core, 3.3 V I/O with 5 V tolerant inputs 384 pin PGBA with 1.0 mm pitch balls ZL30226, ZL30227 and ZL30228 share the same product package and pin-out configuration
Applications
Provides cost effective solutions to implement IMA and/or TC functions over xDSL transport facilities in broadband access networks. Typical applications are for trunking or subscriber access in: * * * Integrated access devices Access multiplexers Next-generation DLC
Overview
The ZL30226, ZL30227 and ZL30228 form a family of similar devices, differing mainly in the maximum number of serial links, and are collectively referred to as ZL30226/7/8. It should be noted throughout this document whenever reference is made to the number of serial links that the ZL30228 offers a maximum of 16 serial links (links 15:0), while the ZL30227 offers a maximum of 8 serial links (links 14, 12, 10, 8, 6, 4, 2 and 0), and the ZL30226 offers a maximum of 4 serial links (links 12, 8, 4 and 0). Pin and register compatibility has been maintained to offer interchangeability. Note: When creating IMA groups for ZL30226 the groups 0,1,2 and 3 should be used.
Description
The ZL30226/7/8 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications. In the ZL30226/7/8 architecture, up to 16 physical and independent serial links can be terminated through the utilization of off-the-shelf xDSL chip sets. The ZL30226/7/8 can provide up to 10 Mb/s per link data rates for TDM serial transmissions for xDSL applications. The ZL30226/7/8 device provides ATM system designers with a flexible architecture when implementing ATM access over existing line interfaces, allowing a migration towards ATM service technology. The ZL30226/7/8 device is compliant with the ATM FORUM IMA specifications for controlling IMA groups of up to 16 lines in a single chip. The ZL30226/7/8 can be configured to operate in different modes to facilitate the implementation of the IMA function at both CPE and Central Office sites. For systems targeting ATM over DSL with IMA and TC operating simultaneously, the ZL30226/7/8 device provides the ideal architecture and capabilities. The device provides up to 8 internal IMA processors and allows for bandwidth scaleability through the use of the UTOPIA MPHY, Level 1 and Level 2 specification at rates up to 52 Mhz. The implementation of IMA as per AF-PHY-0086.001 Inverse Multiplexing for ATM (IMA) Specification Version 1.1 is divided into hardware and software functions. Hardware functions are implemented in the ZL30226/7/8 device and software functions are implemented by the IMA Core (Zarlink or user) software. Additional hardware functions are included to assist in the collection of statistical information to support MIB implementation.
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Zarlink Semiconductor Inc.
ZL30226/7/8
Hardware functions that are implemented in the ZL30226/7/8 device are: * * * * * * * * * Utopia Level 1 or 2 compatible MPHY Interface Incoming HEC verification and correction (optional) Generation of a new HEC byte Format outgoing cells into multi-vendor serial TDM formats Retrieve ATM Cells from the incoming multi-vendor serial TDM format Perform cell delineation Cell pre-processing Provide various counters to assist in performance monitoring TDM expansion ring to span multiple devices
Data Sheet
Hardware functions that are implemented by the IMA processor in the ZL30226/7/8 device are: * * * * * * * * * * * Transmit scheduler (one per IMA group) Generation of the TX IMA Data Cell Rate clock Generation and insertion of ICP cells, Filler Cells and Stuff Cells in IMA mode and Idle Cells in TC mode; the ICP cells are programmed by the user and the Filler and Idle cells are pre-defined Perform IMA Frame synchronization Retrieve and process Rx ICP cells in IMA Mode Management of RX links to be part of the internal re-sequencer when active Extraction of RX IMA Data Cell Rate clock Verification of delays between links Perform re-sequencing of ATM cells using external asynchronous Static RAM Can accommodate more than 200 msec of link differential delay depending on the amount of external memory Provide structured Interrupt scheme to report various events
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Zarlink Semiconductor Inc.
ZL30226/7/8 Table of Contents
Data Sheet
1.0 Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.1 Software Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.1.1 Link State Machines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.1.2 IMA Group State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.1.3 Link Addition, Removal or Restoration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.1.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.1.5 Signalling and Rate Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.1.6 Performance Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.2 Hardware Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.0 The ATM Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.1 Cell In Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2 The ATM Transmission Convergence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.1 TX Cell RAM and TX FIFO Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.3 Parallel to Serial TDM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4 ATM Transmit Path in IMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4.1 IMA Frame Length (M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4.2 Position of the ICP Cell in the IMA Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4.3 Transmit Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4.4 Stuff Cell Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4.5 IMA Data Cell Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.4.6 IMA Controller (RoundRobin Scheduler) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.4.7 ICP Cell Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.4.8 IMA Frame Programmable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4.9 Filler Cell Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4.10 TX IMA Group Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.4.11 TX Link Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.4.12 TX Link Deletion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.5 ATM Transmit Path in TC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.0 The ATM Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.1 Cell Delineation Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.2 De-Scrambling and ATM Cell Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.3 ATM Receive Path in IMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.1 ICP Cell Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.2 IMA Frame Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.3 Link Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.4 RX OAM Label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.5 Out of IMA Frame (OIF) Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.6 Loss of IMA Frame (LIF) Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.7 Filler Cell Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.8 Stuff Cell Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.9 Received ICP Cell Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.10 Rate Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3.11 Cell Buffer/RAM Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3.12 Cell Sequence Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3.13 Delay Between Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3.13.1 RX Recombiner Delay Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3.13.2 RX Maximum Operational Delay Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.13.3 Link Out of Delay Synchronization (LODS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.13.4 Negative Delay Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.13.5 Measured Delay Between Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3.13.6 Incrementing/Decrementing the Recombiner Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3.14 RX IMA Group Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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ZL30226/7/8 Table of Contents
Data Sheet
3.3.15 Link Addition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.3.16 Link Deletion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.3.17 Disabling an IMA Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.4 The ATM Receive Path in TC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.0 Description of the TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.1 Non-Framed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.1.1 Non-Framed Mode - 2.5 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.1.2 Non-Framed Mode - 5.0 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.1.3 Non-Framed Mode - 10.0 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.2 Clock format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.3 TDM Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.4 .Serial to Parallel (S/P) and Parallel to Serial (P/S) Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.5 Clocking Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.5.1 Primary and Secondary Reference Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.5.2 Verification of Clock Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.5.3 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.0 UTOPIA Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.1 ATM Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2 ATM Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3 UTOPIA Operation With a Single PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.4 UTOPIA Operation with Multiple PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.5 UTOPIA Operation in TC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.6 UTOPIA Operation in IMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.7 UTOPIA Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.8 Examples of UTOPIA Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.0 Support Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.1 Counter Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.1.1 UTOPIA Input I/F counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.1.2 Transmit TDM I/F Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.1.3 Receive TDM I/F Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.1.4 Access to the Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.1.5 Latching counter mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.2 Interrupt Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.2.1 IRQ Master Status and IRQ Master Enable Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.2.2 IRQ Link Status and IRQ Link Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.2.2.1 Bit 8 and 7 of IRQ Link 0 Status and IRQ Link 0 Enable Registers. . . . . . . . . . . . . . . . . . . . 65 6.2.3 IRQ Link TC Overflow Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.2.4 IRQ IMA Group Overflow Status and Enable Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.2.5 IRQ IMA Overflow Status and RX UTOPIA IMA Group FIFO Overflow Enable Registers . . . . . . . 66 6.3 Microprocessor Interface Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.3.1 Access to the Various Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.3.2 Direct Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.3 Indirect Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.4 Clearing of Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.4.1 Toggle Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.4 Cell Preprocessor Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.5 TDM Ring Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.6 SRAM decoding for ZL30226 and ZL30227 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.0 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.1 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.2 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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8.0 AC/DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8.1 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.0 List of Abbreviations and Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10.0 ATM Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
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Figure 1 - ZL30226/7/8 Block Diagram with Built-in IMA functions for up to 8 IMA Groups over 4/8/16 links . . . . . 1 Figure 2 - ZL30226 Pinout (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3 - ZL30227 Pinout (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4 - ZL30228 Pinout (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5 - ZL30228 Functional Block Diagram -Transmitter in IMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 6 - Functional Block Diagram of the Transmitter in TC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 7 - Cell Delineation State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 8 - SYNC State Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 9 - ZL30228 Receiver Circuit in IMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 10 - Example of TC Mode Operation (Using Four of Sixteen Possible UTOPIA-Output Ports) . . . . . . . . . 53 Figure 11 - TXCK Output Pin Source Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 12 - ATM Interface to ZL30228 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 13 - ATM Interface to Multiple ZL30228s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 14 - ATM Mixed-Mode Interface to One ZL30228. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 15 - IRQ Register Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 16 - Processed RX Cell FIFO Word Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 17 - Interface to SHDSL Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Figure 18 - Setup and Hold Time Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure 19 - Tri-State Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure 20 - Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure 21 - External Memory Interface Timing - Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Figure 22 - External Memory Interface Timing - Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Figure 23 - CPU Interface Motorola Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Figure 24 - CPU Interface Intel Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Figure 25 - CPU Interface Motorola Timing - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Figure 26 - CPU Interface Intel Timing - Write Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Figure 27 - Serial TDM Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 28 - TDM Ring TX Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Figure 29 - TDM Ring RX Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Figure 30 - JTAG Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Figure 31 - System Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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Data Sheet
Table 1 - IDCR Integration Register Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 2 - ICP Cell Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 3 - Cell Acquisition Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 4 - Differential Delay for Various Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 5 - Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 6 - UTOPIA Output Link Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 7 - UTOPIA Output Group Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 8 - UTOPIA Output Link PHY Enable Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 9 - UTOPIA Output Group PHY Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 10 - UTOPIA Output User Defined Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 11 - UTOPIA Input Link Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 12 - UTOPIA Input Group Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 13 - UTOPIA Input Link PHY Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 14 - UTOPIA Input Group PHY Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 15 - UTOPIA Input Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 16 - UTOPIA Input Parity Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 17 - TX Cell RAM Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 18 - TX ICP Cell Handler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 19 - TX IMA Frame Indication Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 20 - TX ICP Cell Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 21 - TX IMA Frame Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 22 - TX Link FIFO Length Definition Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 23 - TX IMA Group FIFO Length Definition Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 24 - TX FIFO Length Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 25 - RX Link Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 26 - Loss of Delineation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 27 - Cell Delineation Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 28 - IMA Frame Delineation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 29 - User Defined RX OAM Label Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 30 - RX OIF Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 31 - RX OIF Counter Clear Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 32 - RX Wrong Filler Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 33 - RX Load Values/Link Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 34 - RX OAM Label Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 35 - RX Link IMA ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 36 - RX ICP Cell Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 37 - RX Link Frame Sequence Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 38 - RX Link SCCI Sequence Number Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 39 - RX Link OIF Counter Value Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 40 - RX Link ID Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 41 - RX State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 42 - IMA Frame State Machine Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 43 - Cell Delineation Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 44 - RX Cell Type RAM Register I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 45 - RX Cell Type RAM Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 46 - RX Cell Process Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 47 - RX Cell Buffer Increment Read Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 48 - RX Cell Level FIFO Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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Table 49 - Processor RX Cell Link FIFO Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 50 - ICP Cell RAM DEBUG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 51 - Processed RX Cell link FIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 52 - Ring Tx Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 53 - Ring Tx Link Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 54 - Ring Rx Link Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 55 - RX Recombiner Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 56 - RX Reference Link Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 57 - RX IDCR Integration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 58 - RX External SRAM Access Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 59 - Increment Delay Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 60 - Decrement Delay Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 61 - RX Recombiner Delay Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 62 - RX External SRAM Read/Write Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 63 - RX Delay Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 64 - RX Delay Link Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 65 - RX Guardband/Delta Delay Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 66 - RX External SRAM Read/Write Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 67 - RX External SRAM Read/Write Address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 68 - SRAM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 69 - RX Maximum Operational Delay Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 70 - RX Delay Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 71 - Enable Recombiner Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 72 - TX Group Control Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 73 - TX ICP Cell Offset Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 74 - TX Link Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 75 - TX IMA Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 76 - TX Add Link Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 77 - TX Link ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 78 - TX Link Active Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 79 - TX IMA Mode Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 80 - Utopia Input Cell Counter Groups Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 81 - UTOPIA Input Cell Counter Links Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 82 - TX IDCR Integration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 83 - IRQ IMA Group Overflow Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 84 - RX UTOPIA IMA Group FIFO Overflow IRQ Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 85 - General Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 86 - Counter Transfer Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 87 - IRQ Link TC Overflow Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 88 - IRQ IMA Overflow Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 89 - Counter Upper Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 90 - Counter Bytes 2 and 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 91 - Select Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 92 - IRQ Master Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 93 - IRQ Link TC Overflow Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 94 - IRQ Link Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 95 - IRQ Link Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 96 - IRQ Master Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
9
Zarlink Semiconductor Inc.
ZL30226/7/8 List of Tables
Data Sheet
Table 97 - IRQ IMA Group Overflow Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 98 - TX IMA ICP Cell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 99 - TDM TX Link Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 100 - TDM TX Mapping (timeslots 15:0) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 101 - TDM TX Mapping (timeslots 31:16) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 102 - TXCK Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 103 - RXCK Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 104 - REFCK Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 105 - PLL Reference Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 106 - TDM RX Link Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 107 - TDM RX Mapping (timeslots 15:0) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 108 - TDM RX Mapping (timeslots 31:16) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 109 - RX Automatic ATM Synchronization Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 110 - RX IMA ICP Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
111 111 112 113 113 114 114 114 115 115 116 116 116 117
10
Zarlink Semiconductor Inc.
ZL30226/7/8
Pin Diagram - ZL30226
The ZL30226 uses a 384 pin PBGA with a 1.0 mm ball pitch.
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
Data Sheet
2
1
A
DSTi[4]
NC
VDD5
NC
NC
IC
TXRing- TXRing- TXRing- sr_cs_1 sr_a[1] sr_a[4] Data[1] Data[5] Sync
VDD5
sr_a[7]
sr_a [11] sr_a [12] sr_a [14] sr_a [13]
sr_a [15] sr_a [16] sr_a [17] V3.3
sr_a [18]
VDD5
sr_d[6]
NC
TMS
Reset
NC
NC
A
B
NC
VSS
IC
NC
IC
NC
DSTi[0] TXRing- TXRing- TXRing- sr_cs_0 sr_a[0] sr_a[3] sr_a[5] sr_a[8] Data[0] Data[4] Data[7] RXCKi [0] VDD5 Latch TXRing- TXRing- VDD5 Clk Data[2] Data[6] Test2 TXRingData[3] V2.5 NC sr_a[2] sr_a[6] sr_a [10] sr_a[9]
sr_d[0] sr_d[3] sr_d[7]
TDI
TRST
Test4
NC
VSS
NC
B
C
NC
NC
VSS
RXCKi [4] VSS
NC
IC
sr_d [1]
sr_d[4]
Test3
TDO
VDD5
NC
VSS
URx URx Data[0] Data[2]
C
D
IC
NC
NC
V3.3
NC
TXRing- sr_we Clk
V3.3
V2.5
sr_d[2] sr_d[5]
TCK
V3.3
VSS
VSS
URx URx URx Data[1] Data[3] Data[4] URx Data[5] VDD5 URx Data[6]
D
E
NC
NC
NC
V3.3
VSS
E
F
VDD5
NC
IC
NC
V3.3
URx URx URx Data[7] Data[8] Data[9]
F
G
RXCKi DSTi[8] [8] VDD5 NC
NC
IC
URxD URxD URxD URxD ata[10] ata[11] ata[12] ata[13] URxD URxD ata[14] ata[15] URx SOC V2.5 URx Clav URxCLK URxA ddr[1] VDD5 URx Par NC VDD5
G
H
NC
NC
H
J
NC
IC
IC
NC
VDD5
J
K
IC
NC
NC
V3.3
URx Enb URxA ddr[3] UTx Data[1]
URxA ddr[0] URxA ddr[4] NC
K
L
NC
RXCKi [12] IC
DSTi [12] NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
URxA ddr[2] UTx Data[0] V3.3
L
M
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
M
N
NC
VDD5
IC
V2.5
VSS
VSS
VSS
VSS
VSS
VSS
UTx UTx UTx Data[2] Data[3] Data[4] UTx Data[6] VDD5 UTx Data[5] UTxD ata[7]
N
P
NC
NC
NC
V3.3
VSS
VSS
VSS
VSS
VSS
VSS
V2.5
P
R
PD
PD
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
UTx UTxD Data[9] ata[10] UTxD ata[13] V3.3 VDD5
UTxD ata[8]
R
T
PD
PD
PD
NC
VSS
VSS
VSS
VSS
VSS
VSS
UTxD UTxD ata[12] ata[11] UTxD UTxD ata[15] ata[14] UTx Clav UTx SOC
T
U
PD
DSTo [12] PD
TXCKio [12] NC
V2.5
UTxPar
U
V
VDD5
PD
UTxClk
UTx Enb
V
W
PD
NC
PD
PD
UTx UTx UTx UTx Addr[2] Addr[3] Addr[1] Addr[0] UTx REFCK VDD5 Addr[4] [0] REFCK REFCK [2] [3] V3.3 VDD5 NC NC
W
Y
NC
PD
PD
DSTo [8] V3.3
Y
AA
TXCKio VDD5 [8] NC PD
PD
REFCK [1]
AA
AB
PD
VSS
PLL PLL REF[1] REF[0] NC Clk
AB
AC
NC
PD
NC
VSS
V3.3
PD
NC
VDD5
NC
V3.3
RXRing RXRing Data[7] Data[4] PD
V2.5
V3.3
up_a [10]
up_a[7]
V2.5
up_irq
NC
up_d [10] up_d [11] up_d [12] up_d [13]
V3.3
VSS
VSS
NC
AC
AD
PD
VDD5
VSS
NC
NC
NC
PD
PD
PD
DSTo [0] NC
VDD5 RXRing up_oe VDD5 Data[1] or up_rd up_a [11]
up_a[6] up_a[3] up_a[0]
up_d [14] up_d [15]
up_d[8] up_d[5] up_d[2]
VSS
NC
Test1
AD
AE
NC
VSS
NC
NC
PD
DSTo [4] TXCKio [4]
NC
NC
PD
RXRing RXRing RXRing up_cs Data[6] Data[3] Data[0]
up_a[8] up_a[4] up_a[1]
VDD5 up_d[6] up_d[4] up_d[1]
VSS
NC
AE
AF
NC
NC
NC
NC
PD
PD
PD
TXCKio RXRing RXRing RXRing RXRing up_r/w up_a[9] up_a[5] up_a[2] VDD5 [0] Data[5] Data[2] Sync Clk or up_wr
up_d[9] up_d[7]
NC
up_d[3] up_d[0]
AF
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 2 - ZL30226 Pinout (Bottom View)
11
Zarlink Semiconductor Inc.
ZL30226/7/8
Pin Diagram - ZL30227
The ZL30227 uses a 384 pin PBGA with a 1.0 mm ball pitch.
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
Data Sheet
2
1
A
DSTi[4]
NC
VDD5
DSTi[2]
NC
IC
TXRing- TXRing- TXRing- sr_cs_1 sr_a[1] sr_a[4] Data[1] Data[5] Sync
VDD5
sr_a[7] sr_a[11] sr_a[15] sr_a[18] VDD5
sr_d[6]
NC
TMS
Reset
NC
NC
A
B
NC
VSS
IC
NC
RXCKi [2] NC
NC
DSTi[0] TXRing- TXRing- TXRing- sr_cs_0 sr_a[0] sr_a[3] sr_a[5] sr_a[8] sr_a[12] sr_a[16] sr_d[0] sr_d[3] sr_d[7] Data[0] Data[4] Data[7] RXCKi [0] VDD5 Latch- TXRing- TXRing- VDD5 Clk Data[2] Data[6] Test2 TXRingData[3] V2.5 NC sr_a[2] sr_a[6] sr_a[10] sr_a[14] sr_a[17] sr_d[1] sr_d[4] Test3
TDI
TRST
Test4
NC
VSS
NC
B
C
NC
NC
VSS
RXCKi [4] VSS
IC
TDO
VDD5
NC
VSS
URxURxData[0] Data[2]
C
D
IC
NC
NC
V3.3
NC
TXRing- sr_we Clk
V3.3
V2.5
sr_a[9] sr_a[13]
V3.3
sr_d[2] sr_d[5]
TCK
V3.3
VSS
VSS
URxURxURxData[1] Data[3] Data[4] URxData[5] VDD5 URxData[6]
D
E
DSTi[6]
NC
NC
V3.3
VSS
E
F
VDD5
NC
RXCKi [6] NC
NC
V3.3
URxURxURxData[7] Data[8] Data[9]
F
G
RXCKi DSTi[8] [8] VDD5 NC
IC
URxURxURxURxData[10 Data[11] Data[12 Data[13 ] ] ] URxURx- URxPar VDD5 Data[14 Data[15 ] ] URxSOC V2.5 URxClav NC VDD5
G
H
NC
NC
H
J
NC
RXCKi [10] NC
IC
DSTi[10 ] V3.3
J
K
IC
NC
URxClk URxEnb URxAddr[0] URxAddr[1] VDD5 URxAddr[3] UTxData[1] URxAddr[4] NC
K
L
NC
RXCKi DSTi[12 [12] ] IC NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
URxAddr[2] UTxData[0] V3.3
L
M
DSTi[14 ] NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
M
N
VDD5
RXCKi [14] NC
V2.5
VSS
VSS
VSS
VSS
VSS
VSS
UTxUTxUTxData[2] Data[3] Data[4] UTxData[6] VDD5 UTxData[5]
N
P
NC
NC
V3.3
VSS
VSS
VSS
VSS
VSS
VSS
V2.5
P
R
PD
PD
NC
DSTo[1 4] NC
VSS
VSS
VSS
VSS
VSS
VSS
UTxUTxUTxUTxData[9] Data[10 Data[8] Data[7] ] UTxVDD5 UTxUTxData[13 Data[12 Data[11] ] ] V3.3 UTxPar UTxUTxData[15 Data[14 ] ] UTxClav UTxAddr[1] UTxSOC UTxAddr[0] NC
R
T
TXCKio [14] PD
PD
PD
VSS
VSS
VSS
VSS
VSS
VSS
T
U
DSTo[1 TXCKio 2] [12] PD NC
V2.5
U
V
VDD5
PD
UTxClk UTxEnb
V
W
PD
DSTo[1 TXCKio 0] [10] PD PD
PD
UTxAddr[2]
UTxAddr[3]
W
Y
NC
DSTo[8]
UTxA- REFCK VDD5 ddr[4] [0] REFCK REFCK [2] [3] V3.3 VDD5 NC
Y
AA
TXCKio VDD5 [8] NC PD
PD
V3.3
REFCK [1]
AA
AB
PD
VSS
PLLPLLREF[1] REF[0] NC Clk
AB
AC
DSTo[6] TXCKio [6] PD VDD5
NC
VSS
V3.3
PD
NC
VDD5
NC
V3.3
RXRing RXRing Data[7] Data[4] PD
V2.5
V3.3
up_a[10 up_a[7] ]
V2.5
up_irq
NC
up_d[10 ]
V3.3
VSS
VSS
NC
AC
AD
VSS
NC
NC
NC
PD
PD
PD
DSTo[0]
VDD5 RXRing up_oe VDD5 up_a[6] up_a[3] up_a[0] up_d[14 up_d[11 up_d[8] up_d[5] up_d[2] Data[1] or up_rd ] ]
VSS
NC
Test1
AD
AE
NC
VSS
NC
NC
PD
DSTo[4]
NC
DSTo[2]
PD
NC
RXRing RXRing RXRing up_cs up_a[11 up_a[8] up_a[4] up_a[1] up_d[15 up_d[12 VDD5 up_d[6] up_d[4] up_d[1] Data[6] Data[3] Data[0] ] ] ] NC
VSS
NC
AE
AF
NC
NC
NC
NC
TXCKio [4]
PD
TXCKio [2]
PD
TXCKio RXRing RXRing RXRing RXRing up_r/w up_a[9] up_a[5] up_a[2] VDD5 up_d[13 up_d[9] up_d[7] [0] Data[5] Data[2] Sync Clk or ] up_wr
up_d[3] up_d[0]
AF
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 3 - ZL30227 Pinout (Bottom View)
12
Zarlink Semiconductor Inc.
ZL30226/7/8
Pin Diagram - ZL30228
The ZL30228 uses a 384 pin PBGA with a 1.0 mm ball pitch.
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
Data Sheet
2
1
A
DSTi[4] RXCKi [3] NC VSS IC
VDD5 DSTi[2]
IC
IC
TXRing- TXRing- TXRing- sr_cs_1 sr_a[1] sr_a[4] Data[1] Data[5] Sync
VDD5
sr_a[7]
sr_a [11] sr_a [12] sr_a [14] sr_a [13]
sr_a [15] sr_a [16] sr_a [17] V3.3
sr_a [18]
VDD5
sr_d[6]
NC
TMS
Reset
NC
NC
A
B
DSTi[3] RXCKi DSTi[1] DSTi[0] TXRing- TXRing- TXRing- sr_cs_0 sr_a[0] sr_a[3] sr_a[5] sr_a[8] [2] Data[0] Data[4] Data[7] RXCKi [4] VSS IC IC RXCKi [0] VDD5 Latch TXRing- TXRing- VDD5 Clk Data[2] Data[6] Test2 TXRingData[3] V2.5 NC sr_a[2] sr_a[6] sr_a [10] sr_a[9]
sr_d[0] sr_d[3] sr_d[7]
TDI
TRST
Test4
NC
VSS
NC
B
C
DSTi[5]
NC
VSS
sr_d [1]
sr_d[4]
Test3
TDO
VDD5
NC
VSS
URx URx Data[0] Data[2]
C
D
IC
IC
NC
V3.3
RXCKi [1]
TXRing- sr_we Clk
V3.3
V2.5
sr_d[2] sr_d[5]
TCK
V3.3
VSS
VSS
URx URx URx Data[1] Data[3] Data[4] URx Data[5] VDD5 URx Data[6]
D
E
DSTi[6]
NC
RXCKi [5]
V3.3
VSS
E
F
VDD5 DSTi[7] RXCKi [6] RXCKi DSTi[8] RXCKi [8] [7] VDD5 RXCKi [9] RXCKi [10] RXCKi [11] RXCKi [12] IC IC
IC
V3.3
URx URx URx Data[7] Data[8] Data[9]
F
G
IC
URxD URxD URxD URxD ata[10] ata[11] ata[12] ata[13] URxD URxD ata[14] ata[15] URx SOC V2.5 URx Clav URxCLK URxA ddr[1] VDD5 URx Par NC VDD5
G
H
DSTi[9]
H
J
IC
IC
DSTi [10] V3.3
VDD5
J
K
IC
DSTi [11] DSTi [12] DSTi [13] RXCKi [14] DSTo [15] NC
URx Enb URxA ddr[3] UTx Data[1]
URxA ddr[0] URxA ddr[4] NC
K
L
IC
NC
VSS
VSS
VSS
VSS
VSS
VSS
URxA ddr[2] UTx Data[0] V3.3
L
M
DSTi [14] IC
RXCKi [13] V2.5
VSS
VSS
VSS
VSS
VSS
VSS
M
N
VDD5
VSS
VSS
VSS
VSS
VSS
VSS
UTx UTx UTx Data[2] Data[3] Data[4] UTx Data[6] VDD5 UTx Data[5] UTxD ata[7]
N
P
DSTi [15] TXCKio [15] TXCKio [14] PD
RXCKi [15] PD
V3.3
VSS
VSS
VSS
VSS
VSS
VSS
V2.5
P
R
DSTo [14] DSTo [13] V2.5
VSS
VSS
VSS
VSS
VSS
VSS
UTx UTxD Data[9] ata[10] UTxD ata[13] V3.3 VDD5
UTxD ata[8]
R
T
PD
TXCKio [13] TXCKio [12] DSTo [11] TXCKio [10] PD
VSS
VSS
VSS
VSS
VSS
VSS
UTxD UTxD ata[12] ata[11] UTxD UTxD ata[15] ata[14] UTx Clav UTx SOC
T
U
DSTo [12] PD
UTxPar
U
V
VDD5
TXCKio [11] PD
UTxClk
UTx Enb
V
W
PD
DSTo [10] TXCKio [9]
UTx UTx UTx UTx Addr[2] Addr[3] Addr[1] Addr[0] UTx REFCK VDD5 Addr[4] [0] REFCK REFCK [2] [3] V3.3 VDD5 NC NC
W
Y
DSTo [9]
DSTo [8] V3.3
Y
AA
TXCKio VDD5 [8] DSTo [7] DSTo [6] PD TXCKio [7] TXCKio [6] VDD5
PD
REFCK [1]
AA
AB
PD
VSS
PLL PLL REF[1] REF[0] NC Clk
AB
AC
DSTo [5] VSS
VSS
V3.3
PD
NC
VDD5
DSTo [1] PD
V3.3
RXRing RXRing Data[7] Data[4] PD
V2.5
V3.3
up_a [10]
up_a[7]
V2.5
up_irq
NC
up_d [10] up_d [11] up_d [12] up_d [13]
V3.3
VSS
VSS
NC
AC
AD
NC
NC
NC
PD
PD
DSTo [0] NC
VDD5 RXRing up_oe VDD5 up_a[6] up_a[3] up_a[0] Data[1] or up_rd up_a [11] up_a[8] up_a[4] up_a[1]
up_d [14] up_d [15]
up_d[8] up_d[5] up_d[2]
VSS
NC
Test1
AD
AE
NC
VSS
NC
NC
TXCKio [5] NC
DSTo [4]
DSTo [3]
DSTo [2]
TXCKio [1] PD
RXRing RXRing RXRing up_cs Data[6] Data[3] Data[0]
VDD5 up_d[6] up_d[4] up_d[1]
VSS
NC
AE
AF
NC
NC
NC
TXCKio TXCKio TXCKio [4] [3] [2]
TXCKio RXRing RXRing RXRing RXRing up_r/w up_a[9] up_a[5] up_a[2] VDD5 [0] Data[5] Data[2] Sync Clk or up_wr
up_d[9] up_d[7]
NC
up_d[3] up_d[0]
AF
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 4 - ZL30228 Pinout (Bottom View)
13
Zarlink Semiconductor Inc.
ZL30226/7/8
ZL30226 Pin Description Pin # Name I/O Description
Data Sheet
ATM Input Port Signals (UTOPIA Transmit Interface) U2,U1,T4,T2, T1,R3,R4,R2, R1,P3,P1,N1, N2,N3,M2,M4 U3 UTxData [15:0] I UTOPIA Transmit Data Bus. 16 (or 8) bit wide data driven from ATM LAYER device to ZL30226. Bit 15 (or 7) is the MSB. All arriving data between the last word (byte) of the previous cell and the first word (byte) of the following cell (indicated by the SOC signal) is ignored. UTxData[15:8] have internal weak pull-downs. UTOPIA Transmit Parity. Odd (or Even) Parity bit generated by the ATM LAYER. The parity bit is sampled on the rising edge of UTxClk. UTxPar has an internal weak pull-down. UTOPIA Transmit Start of Cell Signal. Active HIGH signal asserted by the ATM LAYER device when TxData[15:0] ([7:0]) contains the first valid word (byte) of the cell. After this signal is high, the following 26 word (52 bytes) should contain valid data. The ZL30226 waits for another TxSOC and TxEnb signal after reading a complete cell. An external pull-down (4.7 K) is strongly recommended. UTOPIA Transmit Clock. Transfer clock from the ATM Layer device to the ZL30226 which synchronizes data transfers on TxData[15:0] ([7:0]). This signal is the clock of the incoming data. Data is sampled on the rising edge of this signal.For 8-bit UTOPIA mode the maximum supported clock is 52 MHz and for 16-bit UTOPIA mode maximum supported clock is 33 MHz. UTOPIA Transmit Data Enable. Active LOW signal asserted by the ATM LAYER device during cycles when TxData contains valid cell data.
UTxPar
I
V1
UTxSOC
I
V4
UTxClk
I
V3 V2
UTxEnb UTxClav
I
O UTOPIA Transmit Cell Available Signal. For cell-level flow control in a MPHY environment, TxClav is an active high tri-stateable signal from the ZL30226 to the ATM LAYER device. I Transmit Address. Five bit wide address bus driven by the ATM layer device to poll and select the appropriate PHY address. TxAddr[4] is the MSB.
Y4,W3,W4, W2,W1
UTxAddr [4:0]
ATM Output Port Signals (UTOPIA Receive Interface) H3,H4,G1,G2, G3,G4,F1,F2, F3,E1,E3,D1, D2,C1,D3,C2 H2 J4 K3 K2 URxData [15:0] O UTOPIA Receive Data Bus. 16 (or 8) bit wide data driven from ZL30226 to ATM layer device. RxData[15] ([7]) is the MSB. To support multiple PHY configurations, RxData is driven only when RxEnb and port is selected. It is tri-stated otherwise. O UTOPIA Receive Parity. Odd (or Even) Parity bit generated by the ZL30226 to the ATM Layer. O UTOPIA Receive Start of Cell Signal. Active high asserted by the ZL30226 when RxData contains the first valid word (byte) of a cell. I I UTOPIA Receive Clock. This signal is the clock driven from the ATM layer to the PHY layer. Data changes after the rising edge of this signal. UTOPIA Receive Data Enable. Active LOW signal asserted by the ATM layer device to indicate that URxData[15:0] ([7:0]) and URxSOC will be sampled at the end of the next cycle. In multiple PHY configurations, URxEnb is used to tri-state URxData and URxSOC ZL30226 outputs. In this case, URxData and URxSOC would be enabled only in cycles following those with URxEnb asserted. In UTOPIA L1, URxEnb must not be tied low and must transition from high (disabled) to low (enabled) to indicate the beginning of data transfer.
URxPar URxSOC URxClk URxEnb
14
Zarlink Semiconductor Inc.
ZL30226/7/8
ZL30226 Pin Description (continued) Pin # J3 Name URxClav I/O Description
Data Sheet
O UTOPIA Receive Cell Available Signal. For cell-level flow control in a MPHY environment, URxClav is an active high tri-stateable signal from the ZL30226 to ATM LAYER device. I Receive Address. Five bit wide address bus driven from the ATM to PHY device to select the appropriate PHY address. URxAddr[4] is the MSB. Receiver Static Memory Interface Signals
L1, L2, L4, L3, K1
URxAddr [4:0]
B7,A7,D8,C8, B8,D9,C9,B9 A9,C10,B10, A10,C11,D11,B 11,A11,C12,D1 2,B12,A12,C13 ,B13,A14,B14, C14,A15,B15 D15 A16,B16
sr_d [7:0] sr_a [18:0]
I/O Static Memory Data Bus. Data Bus to exchange data between the ZL30226 and the external static memory. sr_d[7:0] has internal weak pull-downs. O Static Memory Address Bus. Address bus on the external static memory.
sr_we sr_cs_1, 0
O Static Memory Read/Not Write. If low, data is written from the ZL30226 to the memory. If high, data is read from the memory to the ZL30226. O Static Memory Chip Select Signal. Active low. Processor Interface Signals
AE8,AD8,AF7, AE7,AD7,AC7, AF6,AD6,AF5, AE5,AD5,AE4, AF3,AD4,AE3, AF2 AE12,AC12, AF11,AE11, AC11,AD11, AF10,AE10, AD10,AF9, AE9,AD9 AF12
up_d [15:0]
I/O Processor Data Bus. Data Bus to exchange data between the ZL30226 and a local processor.
up_a [11:0]
I
Processor Address Bus. Used to select the internal registers and memory locations of the ZL30226.
up_r/w or up_wr
I
Processor Read/Not Write (Motorola Mode). This is an input signal. If low, data is written from the processor to the ZL30226. If high, data is read from the ZL30226 to the processor. Processor Not Write (Intel Mode). This is an input signal, active low. If low, data is written from the processor to the ZL30226. Output enable (Motorola Mode). This is an input signal. This signal should be tied to GND for Motorola timing mode. Processor Read (Intel Mode). This is an input signal, active low. If low, data is read from the ZL30226.
AD13
up_oe or up_rd
I
AE13
up_cs
I
Chip Select. This is an active low input signal. If this signal is high, the ZL30226 ignores all other signals on its processor bus. If this signal is low, the ZL30226 accepts the signals on its processor bus.
AC9
up_irq
O Processor Interrupt Request. Open drain signal. If this signal is low, the ZL30226 signals to the processor that an interrupt condition is pending inside the ZL30226.
15
Zarlink Semiconductor Inc.
ZL30226/7/8
ZL30226 Pin Description (continued) Pin # Name I/O Description TDM Interface Signals U25, Y23, AE21, AD17 L24, G25, A25, B20 U24, AA26, AF21, AF17 DSTo [12] [8] [4] [0] DSTi [12] [8] [4] [0] TXCKio [12] [8] [4] [0] RXCKi [12] [8] [4] [0] PLLREF [1:0] REFCK [3:0]
Data Sheet
O Serial TDM Data Output 12, 8, 4, and 0. Serial stream which contains transmit data. The output is set to high impedance for unused time slots and if the link is not used. It is aligned with TXCKio.
I
Serial TDM Data Input 12, 8, 4, and 0. Serial stream which contains receive data. It is aligned with RXCKi. These pins have internal weak pull-downs.
I/O TDM Interface Transmit Clock 12, 8, 4, and 0. This pin is an input or an output as selected by the TDM TX Link Control registers. The TXCK source is software selectable and can be either one of the four RXCK or one of the four REFCK signals when defined as output. When defined as input, the proper clock signal is provided to the input pin. The clock polarity is determined by the TDM TX Link Control registers. These pins have internal weak pull-downs. I TDM Interface Receive Clock 12, 8, 4, and 0. This input line represents the clock for the receive serial TDM data. The expected frequency value to be received at this input clock is defined by the user through the RX Link TDM Control register. These pins have internal weak pull-downs.
L25, G26, C23, C20 AB2,AB1 AA3,AA4, AA1,Y3
O Output reference to an external PLL. I Input Reference Clock inputs 3 to 0. Receive the de-jittered transmit clock reference to be internally routed to the TXCKio transmit clocks. These pins have internal weak pull-downs. TDM Ring Signals
D16
TXRingClk
O TDM Ring TX Clock. Clock output signal used to align the TXRingSync and TXRingData. Should be connected to the RXRingClk input of the next ZL30226 device in the Ring. This output is in High Z state if the TDM Ring is not used. O TDM Ring TX Sync. Synchronization output signal used to retrieve data and control from the bytes on TXRingData. Should be connected to the RXRingSync input of the next ZL30226 device in the Ring. This output is in High Z state if the TDM Ring is not used. O TDM Ring TX Data[7:0]. Data Bus connecting the TX TDM Ring port to the RX TDM Ring port. Should be connected to the RXRingData inputs of the next ZL30226 device in the Ring. These output are in High Z state if the TDM Ring is not used. I TDM Ring RX Clock. Clock input signal used to align the RXRingSync and RXRingData. Should be connected to the TXRingClk input of the previous ZL30226 device in the Ring. There is an internal weak pull-down on this input. TDM Ring RX Sync. Synchronization input signal used to retrieve data and control from the bytes on RXRingData. Should be connected to the TXRingSync output of the previous ZL30226 device in the Ring. There is an internal weak pull-down on this input.
A17
TXRing Sync
B17,C17,A18, B18,D18,C18, A19,B19 AF13
TXRing Data[7:0]
RXRingClk
AF14
RXRing Sync
I
16
Zarlink Semiconductor Inc.
ZL30226/7/8
ZL30226 Pin Description (continued) Pin # AC16,AE16, AF16,AC15, AE15,AF15, AD14,AE14 Name RXRing Data[7:0] I/O I Description
Data Sheet
TDM Ring RX Data[7:0]. Data Bus connecting the RX TDM Ring port to the TX TDM Ring port. Should be connected to the TXRingData inputs of the previous ZL30226 device in the Ring. There are internal weak pull-downs on these inputs. System Signals
AC1 C19
Clk LatchClk
I I
System Clock (50 MHz nominal). In the ZL30226, this clock is used for all internal operations of the device. Counter Latch Clock. The clock present at this input can be divided internally to produce the latch signal for the internal counters. Refer to the Counter Transfer Command register for more details. This pin has an internal pull-down. System Reset. This is an active low input signal. It causes the device to enter the initial state. The Clk signal must be active to reset the internal registers. JTAG Test Clock. TCK should be pulled down if not used. JTAG Test Mode Select. TMS is sampled on the rising edge of TCK. JTAG Test Data Input. This pin has an internal weak pull-down. JTAG Test Reset (active low). Should be asserted LOW on power-up and during reset. Must be HIGH for JTAG boundary-scan operation. This pin has an internal weak pull-down. Test1. Must be tied Low Test3. Must be pulled up to V3.3 for normal operation. NOT 5 V TOLERANT. Power Signals
A4 D7 A5 B6 C6 B5
Reset TCK TMS TDI TDO TRST
I I I I I
O JTAG Test Data Output. Note: TDO is tristated by TRST pin.
AD1 D19 C7 B4
Test1 Test2 Test3 Test4
I I
O Test2. Must be left not connected (NC). O Test4. Must be left not connected (NC)
E2,H1,J1,M3, P2,T3,Y2,AB3, AE6,AF8, AD12,AD15, AC19,AD25, AA25,V26, N25,H26,F26, A23,D20,C16, A13,A8,C5 AA23,AB04, AC06,AC13, AC17,AC22, D6,D10,D14, D22,E23,F4, K23,N4,P23, U4 D13,D17,N23, U23,AC10, AC14,K4,P4
VDD5
S
5 Volt supply pin. Connect to a 5 volt supply when interfacing to 5 volt signals, otherwise, connect to a 3.3 Volt supply.
V3.3
S
3.3 Volt supply pin for I/O pins. Connect to a 3.3 Volt supply.
V2.5
S
2.5 Volt supply for core. Connect to a 2.5 Volt power supply.
17
Zarlink Semiconductor Inc.
ZL30226/7/8
ZL30226 Pin Description (continued) Pin # AB23,AC4, AC5,AC23, AD3,AD24, AE2,AE25,B2, B25,C3,C24, D4,D5,D23,E4, L11,L12,L13, L14,L15,L16, M11,M12,M13, M14,M15,M16, N11,N12,N13, N14,N15,N16, P11,P12,P13,P 14,P15,P16,R1 1,R12,R13,R1 4,R15,R16,T11 ,T12,T13, T14,T15,T16 B1,J2,M1,Y1, AA2,AC2,AD2, AE1,AC3,AF4, AC8,AE17, AC20,AD21, AF22,AF23, AD22,AE23, AF24,AE24, AF25,AD23, AE26,R24, L23,E25,C25, B26,D24,C15, A6,A3,C4, B3,A2 P24,T23, V24,Y26, AB26, AC24, AE20, AC18 R23, W25, AC26, AE19, P26, M24, K24, H23, F25, C26, B23, B21, M26, J23, E26,A22, N26, L26, J26, H24, F23, D25, C22, A21, P25, M23, K25, H25, G24, E24, A24, D21 Name VSS I/O S Ground. Description
Data Sheet
NC
I
Not Connected.
18
Zarlink Semiconductor Inc.
ZL30226/7/8
ZL30226 Pin Description (continued) Pin # R26, T26, T24, V23, W24,Y25, AB25, AC25, AE22, AF20, AF19, AE18, R25,T25,U26, V25,W26,W23, Y24,AA24, AB24,AD26, AC21,AD20, AD19,AD18, AF18,AD16 M25, K26, J24, G23, D26, B24, C21, A20, N24, J25, F24, B22 Name PD I/O Description
Data Sheet
I/O Pull Down. Connect to VSS via a high value resistor, e.g., 10 k ohm.
IC
I
Internal Connection. Connect directly VSS.
19
Zarlink Semiconductor Inc.
ZL30226/7/8
ZL30227 Pin Description Pin # Name I/O Description
Data Sheet
ATM Input Port Signals (UTOPIA Transmit Interface) U2,U1,T4,T2, T1,R3,R4,R2, R1,P3,P1,N1, N2,N3,M2,M4 U3 UTxData [15:0] I UTOPIA Transmit Data Bus. 16 (or 8) bit wide data driven from ATM LAYER device to ZL30227. Bit 15 (or 7) is the MSB. All arriving data between the last word (byte) of the previous cell and the first word (byte) of the following cell (indicated by the SOC signal) is ignored. UTxData[15:8] have internal weak pull-downs. UTOPIA Transmit Parity. Odd (or Even) Parity bit generated by the ATM LAYER. The parity bit is sampled on the rising edge of UTxClk. UTxPar has an internal weak pull-down. UTOPIA Transmit Start of Cell Signal. Active HIGH signal asserted by the ATM LAYER device when TxData[15:0] ([7:0]) contains the first valid word (byte) of the cell. After this signal is high, the following 26 word (52 bytes) should contain valid data. The ZL30227 waits for another TxSOC and TxEnb signal after reading a complete cell.An external pull-down(4.7 K) is strongly recommended. UTOPIA Transmit Clock. Transfer clock from the ATM Layer device to the ZL30227 which synchronizes data transfers on TxData[15:0] ([7:0]). This signal is the clock of the incoming data. Data is sampled on the rising edge of this signal.For 8-bit UTOPIA mode the maximum supported clock is 52 MHz and for 16-bit UTOPIA mode maximum supported clock is 33 MHz. UTOPIA Transmit Data Enable. Active LOW signal asserted by the ATM LAYER device during cycles when TxData contains valid cell data.
UTxPar
I
V1
UTxSOC
I
V4
UTxClk
I
V3 V2
UTxEnb UTxClav
I
O UTOPIA Transmit Cell Available Signal. For cell-level flow control in a MPHY environment, TxClav is an active high tri-stateable signal from the ZL30227 to the ATM LAYER device. I Transmit Address.Five bit wide address bus driven by the ATM layer device to poll and select the appropriate PHY address. TxAddr[4] is the MSB.
Y4,W3,W4, W2,W1
UTxAddr [4:0]
ATM Output Port Signals (UTOPIA Receive Interface) H3,H4,G1,G2, G3,G4,F1,F2, F3,E1,E3,D1, D2,C1,D3,C2 H2 J4 K3 URxData [15:0] O UTOPIA Receive Data Bus. 16 (or 8) bit wide data driven from ZL30227 to ATM layer device. RxData[15] ([7]) is the MSB. To support multiple PHY configurations, RxData is driven only when RxEnb and port is selected. It is tri-stated otherwise. O UTOPIA Receive Parity. Odd (or Even) Parity bit generated by the ZL30227 to the ATM Layer. O UTOPIA Receive Start of Cell Signal. Active high asserted by the ZL30227 when RxData contains the first valid word (byte) of a cell. I UTOPIA Receive Clock. This signal is the clock driven from the ATM layer to the PHY layer. Data changes after the rising edge of this signal.
URxPar URxSOC URxClk
20
Zarlink Semiconductor Inc.
ZL30226/7/8
ZL30227 Pin Description (continued) Pin # K2 Name URxEnb I/O I Description
Data Sheet
UTOPIA Receive Data Enable. Active LOW signal asserted by the ATM layer device to indicate that URxData[15:0] ([7:0]) and URxSOC will be sampled at the end of the next cycle. In multiple PHY configurations, URxEnb is used to tri-state URxData and URxSOC ZL30227 outputs. In this case, URxData and URxSOC would be enabled only in cycles following those with URxEnb asserted. In UTOPIA L1, URxEnb must not be tied low and must transition from high (disabled) to low (enabled) to indicate the beginning of data transfer.
J3
URxClav
O UTOPIA Receive Cell Available Signal. For cell-level flow control in a MPHY environment, URxClav is an active high tri-stateable signal from the ZL30227 to ATM LAYER device. I Receive Address. Five bit wide address bus driven from the ATM to PHY device to select the appropriate PHY address. URxAddr[4] is the MSB.
L1, L2, L4, L3, K1
URxAddr [4:0]
Receiver Static Memory Interface Signals B7,A7,D8,C8, B8,D9,C9,B9 A9,C10,B10, A10,C11,D11,B 11,A11,C12,D1 2,B12,A12,C13 ,B13,A14,B14, C14,A15,B15 D15 A16,B16 sr_d [7:0] sr_a [18:0] I/O Static Memory Data Bus. Data Bus to exchange data between the ZL30227 and the external static memory. sr_d[7:0] has internal weak pull-downs. O Static Memory Address Bus. Address bus on the external static memory.
sr_we sr_cs_1, 0
O Static Memory Read/Not Write. If low, data is written from the ZL30227 to the memory. If high, data is read from the memory to the ZL30227. O Static Memory Chip Select Signal. Active low. Processor Interface Signals
AE8,AD8,AF7, AE7,AD7,AC7, AF6,AD6,AF5, AE5,AD5,AE4, AF3,AD4,AE3, AF2 AE12,AC12, AF11,AE11, AC11,AD11, AF10,AE10, AD10,AF9, AE9,AD9 AF12
up_d [15:0]
I/O Processor Data Bus. Data Bus to exchange data between the ZL30227 and a local processor.
up_a [11:0]
I
Processor Address Bus. Used to select the internal registers and memory locations of the ZL30227.
up_r/w or up_wr
I
Processor Read/Not Write. Motorola Mode. This is an input signal. If low, data is written from the processor to the ZL30227. If high, data is read from the ZL30227 to the processor. Processor Not Write (Intel Mode). This is an input signal, active low. If low, data is written from the processor to the ZL30227.
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Zarlink Semiconductor Inc.
ZL30226/7/8
ZL30227 Pin Description (continued) Pin # AD13 Name up_oe or up_rd I/O I Description
Data Sheet
Output enable (Motorola Mode). This is an input signal. This signal should be tied to GND for Motorola timing mode. Processor Read (Intel Mode). This is an input signal, active low. If low, data is read from the ZL30227.
AE13
up_cs
I
Chip Select. This is an active low input signal. If this signal is high, the ZL30227 ignores all other signals on its processor bus. If this signal is low, the ZL30227 accepts the signals on its processor bus.
AC9
up_irq
O Processor Interrupt Request. Open drain signal. If this signal is low, the ZL30227 signals to the processor that an interrupt condition is pending inside the ZL30227. TDM Interface Signals
R23 U25 W25 Y23 AC26 AE21 AE19 AD17 M26 L24 J23 G25 E26 A25 A22 B20 T26 U24 W24 AA26 AC25 AF21 AF19 AF17 N24 L25 J25 G26 F24 C23 B22 C20
DSTo [14] [12] [10] [8] [6] [4] [2] [0] DSTi [14] [12] [10] [8] [6] [4] [2] [0] TXCKio [14] [12] [10] [8] [6] [4] [2] [0 RXCKi [14] [12] [10] [8] [6] [4] [2] [0]
O Serial TDM Data Output. Serial stream which contains transmit data. The output is set to high impedance for unused time slots and if the link is not used. It is aligned with TXCKio.
I
Serial TDM Data Input. Serial stream which contains receive data. It is aligned with RXCKi. These pins have internal weak pull-downs.
I/O TDM Interface Transmit Clock. This pin is an input or an output as selected by the TDM TX Link Control registers. The TXCK source is software selectable and can be either one of the eight RXCK or one of the four REFCK signals when defined as output. When defined as input, the proper clock signal is provided to the input pin. The clock polarity is determined by the TDM TX Link Control registers. These pins have internal weak pull-downs.
I
TDM Interface Receive Clock. This input line represents the clock for the receive serial TDM data. The expected frequency value to be received at this input clock is defined by the user through the RX Link TDM Control register. These pins have internal weak pull-downs.
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Zarlink Semiconductor Inc.
ZL30226/7/8
ZL30227 Pin Description (continued) Pin # AB2,AB1 AA3,AA4, AA1,Y3 Name PLLREF [1:0] REFCK [3:0] I/O Description
Data Sheet
O Output reference to an external PLL. I Input Reference Clock inputs 3 to 0. Receive the de-jittered transmit clock reference to be internally routed to the TXCKio transmit clocks. These pins have internal weak pull-downs. TDM Ring Signals
D16
TXRingClk
O TDM Ring TX Clock. Clock output signal used to align the TXRingSync and TXRingData. Should be connected to the RXRingClk input of the next ZL30227 device in the Ring. This output is in High Z state if the TDM Ring is not used.
A17
TXRingSync O TDM Ring TX Sync. Synchronization output signal used to retrieve data and control from the bytes on TXRingData. Should be connected to the RXRingSync input of the next ZL30227 device in the Ring. This output is in High Z state if the TDM Ring is not used. O TDM Ring TX Data[7:0]. Data Bus connecting the TX TDM Ring port to the RX TDM Ring port. Should be connected to the RXRingData inputs of the next ZL30227 device in the Ring. These output are in High Z state if the TDM Ring is not used. I TDM Ring RX Clock. Clock input signal used to align the RXRingSync and RXRingData. Should be connected to the TXRingClk input of the previous ZL30227 device in the Ring. There is an internal weak pull-down on this input. TDM Ring RX Sync. Synchronization input signal used to retrieve data and control from the bytes on RXRingData. Should be connected to the TXRingSync output of the previous ZL30227 device in the Ring. There is an internal weak pull-down on this input. TDM Ring RX Data[7:0]. Data Bus connecting the RX TDM Ring port to the TX TDM Ring port. Should be connected to the TXRingData inputs of the previous ZL30227 device in the Ring. There are internal weak pull-downs on these inputs. System Signals
B17,C17,A18, TXRingData B18,D18,C18, [7:0] A19,B19 AF13 RXRingClk
AF14
RXRingSync
I
AC16,AE16, AF16,AC15, AE15,AF15, AD14,AE14
RXRingData [7:0]
I
AC1 C19
Clk LatchClk
I I
System Clock (50 MHz nominal). In the ZL30227, this clock is used for all internal operations of the device. Counter Latch Clock. The clock present at this input can be divided internally to produce the latch signal for the internal counters. Refer to the Counter Transfer Command register for more details. This pin has an internal pull-down. System Reset. This is an active low input signal. It causes the device to enter the initial state. The Clk signal must be active to reset the internal registers. JTAG Test Clock. TCK should be pulled down if not used. JTAG Test Mode Select. TMS is sampled on the rising edge of TCK. JTAG Test Data Input. This pin has an internal weak pull-down.
A4 D7 A5 B6 C6
Reset TCK TMS TDI TDO
I I I I
O JTAG Test Data Output. Note: TDO is tristated by TRST pin.
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Zarlink Semiconductor Inc.
ZL30226/7/8
ZL30227 Pin Description (continued) Pin # B5 Name TRST I/O I Description
Data Sheet
JTAG Test Reset (active low). Should be asserted LOW on power-up and during reset. Must be HIGH for JTAG boundary-scan operation. This pin has an internal weak pull-down. Test1. Must be tied Low.
AD1 D19 C7 B4
Test1 Test2 Test3 Test4
I
O Test2. Must be left not connected (NC). I Test3. Must be pulled up to V3.3 for normal operation. NOT 5 V TOLERANT.
O Test4. Must be left not connected (NC). Power Signals
E2,H1,J1,M3, P2,T3,Y2,AB3, AE6,AF8, AD12,AD15, AC19,AD25, AA25,V26, N25,H26,F26, A23,D20,C16, A13,A8,C5 AA23,AB04, AC06,AC13, AC17,AC22, D6,D10,D14, D22,E23,F4, K23,N4,P23, U4 D13,D17,N23, U23,AC10, AC14,K4,P4 AB23,AC4, AC5,AC23, AD3,AD24, AE2,AE25,B2, B25,C3,C24, D4,D5,D23,E4, L11,L12,L13, L14,L15,L16, M11,M12,M13, M14,M15,M16, N11,N12,N13, N14,N15,N16, P11,P12,P13,P 14,P15,P16, R11,R12,R13, R14,R15,R16, T11,T12,T13, T14,T15,T16
VDD5
S 5 Volt supply pin. Connect to a 5 volt supply when interfacing to 5 volt signals, otherwise, connect to a 3.3 Volt supply.
V3.3
S 3.3 Volt supply pin for I/O pins. Connect to a 3.3 Volt supply.
V2.5
S 2.5 Volt supply for core. Connect to a 2.5 Volt power supply.
VSS
S Ground.
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Zarlink Semiconductor Inc.
ZL30226/7/8
ZL30227 Pin Description (continued) Pin # B1,J2,M1,Y1, AA2,AC2,AD2, AE1,AC3,AF4, AC8,AE17, AC20,AD21, AF22,AF23, AD22,AE23, AF24,AE24, AF25,AD23, AE26,R24, L23,E25,C25, B26,D24,C15, A6,A3,C4, B3,A2 P24, T23, V24,Y26, AB26, AC24, AE20,AC18 P26, M24, K24, H23, F25, C26, B23, B21 N26, L26, J26, H24, F23, D25, C22, A21, P25, M23, K25, H25, G24, E24, A24, D21 R26, T24, V23, Y25, AB25, AE22, AF20, AE18, R25,T25,U26, V25,W26,W23, Y24,AA24, AB24,AD26, AC21,AD20, AD19,AD18, AF18,AD16 M25, K26, J24, G23, D26, B24, C21, A20 Name NC I/O I Not Connected. Description
Data Sheet
PD
Pull-down. Connect to VSS via a high value resistor e.g., 10 k ohm.
IC
I
Internal Connection. Connect directly VSS.
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Zarlink Semiconductor Inc.
ZL30226/7/8
ZL30228 Pin Description Pin # Name I/O Description
Data Sheet
ATM Input Port Signals (UTOPIA Transmit Interface) U2,U1,T4,T2, T1,R3,R4,R2, R1,P3,P1,N1, N2,N3,M2,M4 U3 UTxData [15:0] I UTOPIA Transmit Data Bus. 16 (or 8) bit wide data driven from ATM LAYER device to ZL30228. Bit 15 (or 7) is the MSB. All arriving data between the last word (byte) of the previous cell and the first word (byte) of the following cell (indicated by the SOC signal) is ignored. UTxData[15:8] have internal weak pull-downs. UTOPIA Transmit Parity. Odd (or Even) Parity bit generated by the ATM LAYER. The parity bit is sampled on the rising edge of UTxClk. UTxPar has an internal weak pull-down. UTOPIA Transmit Start of Cell Signal. Active HIGH signal asserted by the ATM LAYER device when TxData[15:0] ([7:0]) contains the first valid word (byte) of the cell. After this signal is high, the following 26 word (52 bytes) should contain valid data. The ZL30228 waits for another TxSOC and TxEnb signal after reading a complete cell.An external pull-down(4.7 K) is strongly recommended. UTOPIA Transmit Clock. Transfer clock from the ATM Layer device to the ZL30228 which synchronizes data transfers on TxData[15:0] ([7:0]). This signal is the clock of the incoming data. Data is sampled on the rising edge of this signal.For 8-bit UTOPIA mode the maximum supported clock is 52 MHz and for 16-bit UTOPIA mode maximum supported clock is 33 MHz. UTOPIA Transmit Data Enable. Active LOW signal asserted by the ATM LAYER device during cycles when TxData contains valid cell data.
UTxPar
I
V1
UTxSOC
I
V4
UTxClk
I
V3 V2
UTxEnb UTxClav
I
O UTOPIA Transmit Cell Available Signal. For cell-level flow control in a MPHY environment, TxClav is an active high tri-stateable signal from the ZL30228 to the ATM LAYER device. I Transmit Address.Five bit wide address bus driven by the ATM layer device to poll and select the appropriate PHY address. TxAddr[4] is the MSB.
Y4,W3,W4, W2,W1
UTxAddr [4:0]
ATM Output Port Signals (UTOPIA Receive Interface) H3,H4,G1,G2, G3,G4,F1,F2, F3,E1,E3,D1, D2,C1,D3,C2 H2 J4 K3 K2 URxData [15:0] O UTOPIA Receive Data Bus. 16 (or 8) bit wide data driven from ZL30228 to ATM layer device. RxData[15] ([7]) is the MSB. To support multiple PHY configurations, RxData is driven only when RxEnb and port is selected. It is tri-stated otherwise. O UTOPIA Receive Parity. Odd (or Even) Parity bit generated by the ZL30228 to the ATM Layer. O UTOPIA Receive Start of Cell Signal. Active high asserted by the ZL30228 when RxData contains the first valid word (byte) of a cell. I I UTOPIA Receive Clock. This signal is the clock driven from the ATM layer to the PHY layer. Data changes after the rising edge of this signal. UTOPIA Receive Data Enable. Active LOW signal asserted by the ATM layer device to indicate that URxData[15:0] ([7:0]) and URxSOC will be sampled at the end of the next cycle. In multiple PHY configurations, URxEnb is used to tri-state URxData and URxSOC ZL30228 outputs. In this case, URxData and URxSOC would be enabled only in cycles following those with URxEnb asserted. In UTOPIA L1, URxEnb must not be tied low and must transition from high (disabled) to low (enabled) to indicate the beginning of data transfer.
URxPar URxSOC URxClk URxEnb
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Zarlink Semiconductor Inc.
ZL30226/7/8
ZL30228 Pin Description (continued) Pin # J3 Name URxClav I/O Description
Data Sheet
O UTOPIA Receive Cell Available Signal. For cell-level flow control in a MPHY environment, URxClav is an active high tri-stateable signal from the ZL30228 to ATM LAYER device. I Receive Address. Five bit wide address bus driven from the ATM to PHY device to select the appropriate PHY address. URxAddr[4] is the MSB.
L1, L2, L4, L3, K1
URxAddr [4:0]
Receiver Static Memory Interface Signals B7,A7,D8,C8, B8,D9,C9,B9 A9,C10,B10, A10,C11,D11, B11,A11,C12, D12,B12,A12, C13,B13,A14, B14,C14,A15, B15 D15 A16,B16 sr_d [7:0] sr_a [18:0] I/O Static Memory Data Bus. Data Bus to exchange data between the ZL30228 and the external static memory. sr_d[7:0] has internal weak pull-downs. O Static Memory Address Bus. Address bus on the external static memory.
sr_we sr_cs_1, 0
O Static Memory Read/Not Write. If low, data is written from the ZL30228 to the memory. If high, data is read from the memory to the ZL30228. O Static Memory Chip Select Signal. Active low. Processor Interface Signals
AE8,AD8,AF7, AE7,AD7,AC7, AF6,AD6, AF5,AE5,AD5, AE4,AF3,AD4, AE3,AF2 AE12,AC12, AF11,AE11, AC11,AD11, AF10,AE10, AD10,AF9, AE9,AD9 AF12
up_d [15:0]
I/O Processor Data Bus. Data Bus to exchange data between the ZL30228 and a local processor.
up_a [11:0]
I
Processor Address Bus. Used to select the internal registers and memory locations of the ZL30228.
up_r/w or up_wr
I
Processor Read/Not Write. Motorola Mode. This is an input signal. If low, data is written from the processor to the ZL30228. If high, data is read from the ZL30228 to the processor. Processor Not Write (Intel Mode). This is an input signal, active low. If low, data is written from the processor to the ZL30228.
AD13
up_oe or up_rd
I
Output enable (Motorola Mode). This is an input signal. This signal should be tied to GND for Motorola timing mode. Processor Read (Intel Mode). This is an input signal, active low. If low, data is read from the ZL30228.
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Zarlink Semiconductor Inc.
ZL30226/7/8
ZL30228 Pin Description (continued) Pin # AE13 Name up_cs I/O I Description
Data Sheet
Chip Select. This is an active low input signal. If this signal is high, the ZL30228 ignores all other signals on its processor bus. If this signal is low, the ZL30228 accepts the signals on its processor bus.
AC9
up_irq
O Processor Interrupt Request. Open drain signal. If this signal is low, the ZL30228 signals to the processor that an interrupt condition is pending inside the ZL30228. TDM Interface Signals
P24,R23,T23, U25,V24,W25, Y26,Y23, AB26,AC26, AC24,AE21, AE20,AE19, AC18,AD17 P26,M26,M24, L24,K24,J23, H23,G25,F25, E26,C26,A25, B23,A22,B21, B20 R26,T26,T24, U24,V23,W24, Y25,AA26, AB25,AC25, AE22,AF21, AF20,AF19, AE18,AF17 P25,N24,M23, L25,K25,J25, H25,G26,G24, F24,E24,C23, A24,B22,D21, C20 AB2,AB1 AA3,AA4, AA1,Y3
DSTo [15:0]
O Serial TDM Data Output 15-0. Serial stream which contains transmit data. The output is set to high impedance for unused time slots and if the link is not used. It is aligned with TXCKio.
DSTi [15:0]
I
Serial TDM Data Input 15-0. Serial stream which contains receive data. It is aligned with RXCKi. These pins have internal weak pull-downs.
TXCKio [15:0]
I/O TDM Interface Transmit Clock 15-0. This pin is an input or an output as selected by the TDM TX Link Control registers. The TXCK source is software selectable and can be either one of the sixteen RXCK or one of the four REFCK signals when defined as output. When defined as input, the proper clock signal is provided to the input pin. The clock polarity is determined by the TDM TX Link Control registers. These pins have internal weak pull-downs. I TDM Interface Receive Clock 15-0. This input line represents the clock for the receive serial TDM data. The expected frequency value to be received at this input clock is defined by the user through the RX Link TDM Control register. These pins have internal weak pull-downs.
RXCKi [15:0]
PLLREF [1:0] REFCK [3:0]
O Output reference to an external PLL. I Input Reference Clock inputs 3 to 0. Receive the de-jittered transmit clock reference to be internally routed to the TXCKio transmit clocks. These pins have internal weak pull-downs. TDM Ring Signals
D16
TXRingClk
O TDM Ring TX Clock. Clock output signal used to align the TXRingSync and TXRingData. Should be connected to the RXRingClk input of the next ZL30228 device in the Ring. This output is in High Z state if the TDM Ring is not used. O TDM Ring TX Sync. Synchronization output signal used to retrieve data and control from the bytes on TXRingData. Should be connected to the RXRingSync input of the next ZL30228 device in the Ring. This output is in High Z state if the TDM Ring is not used.
A17
TXRingSync
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Zarlink Semiconductor Inc.
ZL30226/7/8
ZL30228 Pin Description (continued) Pin # Name I/O Description
Data Sheet
B17,C17,A18, TXRingData B18,D18,C18, [7:0] A19,B19 AF13 RXRingClk
O TDM Ring TX Data[7:0]. Data Bus connecting the TX TDM Ring port to the RX TDM Ring port. Should be connected to the RXRingData inputs of the next ZL30228 device in the Ring. These output are in High Z state if the TDM Ring is not used. I TDM Ring RX Clock. Clock input signal used to align the RXRingSync and RXRingData. Should be connected to the TXRingClk input of the previous ZL30228 device in the Ring. There is an internal weak pull-down on this input. TDM Ring RX Sync. Synchronization input signal used to retrieve data and control from the bytes on RXRingData. Should be connected to the TXRingSync output of the previous ZL30228 device in the Ring. There is an internal weak pull-down on this input. TDM Ring RX Data[7:0]. Data Bus connecting the RX TDM Ring port to the TX TDM Ring port. Should be connected to the TXRingData inputs of the previous ZL30228 device in the Ring. There are internal weak pull-downs on these inputs. System Signals
AF14
RXRingSync
I
AC16,AE16, AF16,AC15, AE15,AF15, AD14,AE14
RXRingData [7:0]
I
AC1 C19
Clk LatchClk
I I
System Clock (50 MHz nominal). In the ZL30228, this clock is used for all internal operations of the device. Counter Latch Clock. The clock present at this input can be divided internally to produce the latch signal for the internal counters. Refer to the Counter Transfer Command register for more details. This pin has an internal pull-down. System Reset. This is an active low input signal. It causes the device to enter the initial state. The Clk signal must be active to reset the internal registers. JTAG Test Clock. TCK should be pulled down if not used. JTAG Test Mode Select. TMS is sampled on the rising edge of TCK. JTAG Test Data Input. This pin has an internal weak pull-down.
A4 D7 A5 B6 C6 B5
Reset TCK TMS TDI TDO TRST
I I I I
O JTAG Test Data Output. Note: TDO is tristated by TRST pin. I JTAG Test Reset (active low). Should be asserted LOW on power-up and during reset. Must be HIGH for JTAG boundary-scan operation. This pin has an internal weak pull-down. Test1. Must be tied Low. Test3. Must be pulled up to V3.3 for normal operation. NOT 5 V TOLERANT. Power Signals
AD1 D19 C7 B4
Test1 Test2 Test3 Test4
I I
O Test2. Must be left not connected (NC). O Test4. Must be left not connected (NC)
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Zarlink Semiconductor Inc.
ZL30226/7/8
ZL30228 Pin Description (continued) Pin # E2,H1,J1,M3, P2,T3,Y2,AB3, AE6,AF8, AD12,AD15, AC19,AD25, AA25,V26, N25,H26,F26, A23,D20,C16, A13,A8,C5 AA23,AB04, AC06,AC13, AC17,AC22, D6,D10,D14, D22,E23,F4, K23,N4,P23, U4 D13,D17,N23, U23,AC10, AC14,K4,P4 AB23,AC4, AC5,AC23, AD3,AD24, AE2,AE25,B2, B25,C3,C24, D4,D5,D23,E4, L11,L12,L13, L14,L15,L16, M11,M12,M13, M14,M15,M16, N11,N12,N13, N14,N15,N16, P11,P12,P13, P14,P15,P16, R11,R12,R13, R14,R15,R16, T11,T12,T13, T14,T15,T16 B1,J2,M1,Y1, AA2,AC2,AD2, AE1,AC3,AF4, AC8,AE17, AC20,AD21, AF22,AF23, AD22,AE23, AF24,AE24, AF25,AD23, AE26,R24, L23,E25,C25, B26,D24,C15, A6,A3,C4, B3,A2 Name VDD5 I/O Description
Data Sheet
S 5 Volt supply pin. Connect to a 5 volt supply when interfacing to 5 volt signals, otherwise, connect to a 3.3 Volt supply.
V3.3
S 3.3 Volt supply pin for I/O pins. Connect to a 3.3 Volt supply.
V2.5
S 2.5 Volt supply for core. Connect to a 2.5 Volt power supply.
VSS
S Ground.
NC
I
Not Connected.
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Zarlink Semiconductor Inc.
ZL30226/7/8
ZL30228 Pin Description (continued) Pin # R25,T25,U26, V25,W26,W23, Y24,AA24, AB24,AD26, AC21,AD20, AD19,AD18, AF18,AD16 N26,M25,L26, K26,J26,J24, H24,G23,F23, D26,D25,B24, C22,C21,A21, A20 Name PD I/O Description
Data Sheet
Pull-down. Connect to VSS via a high value resistor, e.g., 10 k ohm.
IC
I
Internal Connection. Connect directly VSS.
1.0
Device Architecture
The ZL30226/7/8, supported by software, implements the ATM Forum Inverse Multiplexing for Asynchronous Transfer Mode (IMA) Specification. Actions are implemented by the ZL30226/7/8 and decisions are made by the software. This approach minimizes the impact of any changes that might occur in the specification. The ZL30226/7/8 supports the following two major modes of operation: * * the IMA mode (as defined by the ATM Forum IMA Specification), both version 1.0 and 1.1 the Transmission Convergence (TC) mode.
Up to eight IMA Groups can be implemented (4 groups - 0,1,2,3 for ZL30226). Any of the available serial (TDM) interfaces can be assigned dynamically to any of these IMA Groups. A different UTOPIA PHY address is assigned to each of the IMA Groups For ZL30226 groups 0, 1, 2 and 3 should be used. The TC mode is used to transfer the cells from the UTOPIA Interface to a serial (TDM) port without any overhead. Up to 16 UTOPIA PHY addresses can be supported in TC mode (one per serial port). The ZL30226/7/8 also supports a mixed mode where the TDM Interfaces not assigned to an IMA Group can be used in TC mode. The IMA implementation is divided into hardware and software functions. The ZL30226/7/8 implements the hardware functions. The software functions are implemented by the user or Zarlink IMA Core. The hardware and software functions are described below. Notice that a number of ZL30226/7/8 functions are included to assist in the collection of statistical information. This information supports the MIB implementation.
1.1
Software Functions
For the ZL30226/7/8 to comply with the IMA specification, the following functions must be implemented by software: * * * * the transmit and receive Link State Machines (LSM) the IMA Group State Machines (GSM) the IMA Group Traffic State Machines (GTSM) the Operations and Maintenance (OAM) functions
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Zarlink Semiconductor Inc.
ZL30226/7/8
1.1.1 Link State Machines
Data Sheet
The software implemented transmit and receive LSMs are independent (i.e., each link has its own LSM). LSMs rely on various events from: the ZL30226/7/8 interface, such as cell errors, excessive delay between-links, etc.; or, from the T1/E1/J1/DSL framer, such as Loss Of Signal (LOS), Loss Of Frame (LOF), Remote Alarm Indication (RAI) etc. On-chip registers are used to generate the ICP cells that communicate the LSM states at the Far End (FE).
1.1.2
IMA Group State Machines
The IMA GSMs and Group Traffic State Machines (GTSM) must be implemented in software. One of each state machine should be implemented for each IMA Group. On-chip registers are used to generate the ICP cells that communicate the various states to the FE.
1.1.3
Link Addition, Removal or Restoration
The addition, removal or restoration of a link is controlled by software using the various control registers in the ZL30226/7/8 and in the xDSL framers. Decisions are based on the ZL30226/7/8 and typically xDSL framer status registers.
1.1.4
Interrupts
The ZL30226/7/8 provides numerous registers and counters to implement a polling and/or interrupt mechanism for tracking link and IMA Group status. This traffic in and out information is used by the Management Information Base (MIB) for each IMA Group.
1.1.5
Signalling and Rate Adjustment
The microprocessor controls the operation of the serial links by providing handshaking between the Far End (FE) and Near End (NE) including such functions as signaling and loopback controls. Rate adjustment is controlled by: * * adding or removing one or more serial links providing feedback to the ATM network for adjusting the ATM traffic.
1.1.6
Performance Monitoring
Software implements most of the performance monitoring. The ZL30226/7/8 provides status information for: * * * * * the Cell Delineation Block and IMA Frame State Machine the number of ICP violations the total number of cells the total number of User cells the number of idle or discarded cells.
It also provides the content for received ICP cells that contain some changes. The external xDSL framers provide the low level status of the link. The software integrates and responds to the various events.
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Zarlink Semiconductor Inc.
ZL30226/7/8
1.2 Hardware Functions
Data Sheet
The ZL30226/7/8 circuitry implements the following functions: * * * * * * * * * * * * * * * * * * UTOPIA L1 and L2 compatible Interface (8-bit mode wide bus supported with UTOPIA clock of up to 52 MHz and 16- bit wide with UTOPIA clock of up to 33 MHz) verification of the incoming HEC (optional) generation of a new HEC byte transmit scheduler generation of the TX IMA Data Cell Rate (IDCR) clock generation and insertion of ICP cells, Filler Cells and Stuff Cells in IMA mode generation of Idle Cells in TC mode (from on-chip copies of the cell) flexible serial link (TDM) formatting of the outgoing bytes retrieval of ATM Cells from the incoming flexible TDM format cell delineation retrieval and processing of ICP cells synchronization of the IMA Frame management of the internal re-sequencer RX links (when active) extraction of the RX IDCR verification of the delays between links re-sequencing of ATM cells using external Static RAM various performance monitoring counters 16-bit microprocessor interface (adaptable to Intel or Motorola interfaces)
The ZL30226/7/8 can be separated into four major independent blocks and five support blocks. The four major independent blocks are: * * * * the ATM Transmit Path the ATM Receive Path the TDM Interface the UTOPIA Interface
The five support blocks are: * * * * * the Counter Block the Interrupt Block the Microprocessor Interface Block the Cell Preprocessor Block the TDM Ring Block
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Zarlink Semiconductor Inc.
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2.0 The ATM Transmit Path
Data Sheet
The transmit path corresponds to a cell flow from the ATM Layer towards the PHY Layer. The ATM cell path on the transmit side starts at the UTOPIA L2 or L1 Interface. Once ATM cells are received at the UTOPIA port, the device transfers these cells to the transmit block. The ZL30226/7/8 provides ATM cell mapping and transmission convergence blocks to transport ATM cells over a maximum of sixteen flexible serial interface ports. These serial interface ports communicate with most off-the-shelf xDSL modems/framers or other low speed link devices. Each of these serial links can be assigned to either an IMA Group or to a TC link. A single serial link cannot be assigned to more than one IMA Group. The ZL30226 supports up to 4 serial links, while the ZL30227 supports up to 8 serial links and the ZL30228 supports up to 16 serial links. The functional block diagram (Figure 5) illustrates the transmit function of the ZL30228.
2.1
Cell In Control
In general terms, the ZL30226/7/8 transmit input port has the following properties: * * * * * * * * * * * * cell level handshaking is compatible with the ATM Forum UTOPIA L1 and L2 Specification behaves like a UTOPIA compatible MPHY Device or Single PHY Device each port can be enabled or disabled independently parity (odd or even) can be checked optionally verifies and then generates the HEC for incoming cells includes the ATM Forum polynomial when generating the HEC (default option that can be disabled) either passes or removes incoming Idle cells either passes or removes incoming Unassigned cells provides a counter per UTOPIA port for the total number of Idle/Unassigned/Filler cells with a valid HEC or optionally the total number of User cells (24 bits/16 bit latched) provides a counter per UTOPIA port for the total number of cells with wrong incoming HEC (24 bits/16 bit latched) provides a counter per UTOPIA port for the total number of cells handled (24 bits/16 bit latched) provides counters for Parity errors
The input port can be enabled to remove (filter) Unassigned or Idle cells. If Unassigned or Idle Cell Filtering is enabled, the device checks for and discards Unassigned or Idle cells. This function is programmed in the UTOPIA Input Control (0x0052) register. Section 5.0 describes the UTOPIA Interface in more detail.
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Zarlink Semiconductor Inc.
ZL30226/7/8
Transmitter Cell RAM FIFO Link 0 (see Note 1) FIFO Link 1 (see Note 1) ICP Cell Mod. and Cell Scrambling ICP Cell Mod. and Cell Scrambling P/S P/S
Data Sheet
ATM In
UTOPIA L2 Interface
Serial Streams Link 0 Link 1
Cell In Control
FIFO Link 15 (see Note 1) from IDCR Generator TX Utopia FIFO Group 0
ICP Cell Mod. and Cell Scrambling
P/S
Link 15 From
TX Utopia FIFO Group 7 Filler Cell Idle Cell ICP Cell Group 0 ICP Cell Group 1
Round Robin Scheduler and FIFO Selection and Adaptive Shaper (1 of 8)
TDM Ring
TDM RING Control
to Cell_In_Control
IDCR Generator (1 of 8)
Transmitter Reference Link Timing
To RX Block
ICP Cell Group 7 ICP Cell Buffer RAM Next ICP Cell Group 0 Next ICP Cell Group 1 Micro I/F Next ICP Cell Group 7 ICP Cell Handler
Note 1: This FIFO is the TX UTOPIA FIFO when the link is configured in non-IMA Mode and it is the TX LINK FIFO when it is configured in IMA Mode. Note 2: In ZL30226 groups 0,1,2 and 3 should be used.
Figure 5 - ZL30228 Functional Block Diagram -Transmitter in IMA Mode
2.2
The ATM Transmission Convergence
The Transmit Convergence (TC) function is common for both the IMA and TC modes. It integrates the circuitry to support ATM cell payload scrambling, HEC generation and the generation of Idle/Filler/ICP cells for use with the xDSL trunks. Each of the available ATM TC circuits can use the polynomial X43 + 1 to scramble the ATM cell payload field. The ZL30226/7/8 ATM cell payload scrambling function can be disabled. The ITU I.432 polynomial X8 + X2 + X + 1 is used to generate the HEC field of the ATM cell. By default, the ATM Forum polynomial X6 + X4 + X2 + 1 is added to the calculated HEC octet. The addition of the ATM Forum polynomial can be disabled. The resulting calculation is then written on the HEC field and the ATM cell is ready (i.e., complies with the IMA transmit protocol) for transmission over the flexible TDM Interface. In cases where the TC block requests a cell to be transferred to any of the serial interfaces and the TX UTOPIA FIFO has no cell ready for transmission, then the TC block will automatically send an IDLE cell (in TC mode) or a Filler cell (in IMA mode) to the line. The default values for the Idle and the Filler cells comply with the ATM IMA Specification and are pre-loaded in the ZL30226/7/8 following a reset. The TX Cell RAM Control (0x0080) register can be used to re-initialize the TX Cell RAM.
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Zarlink Semiconductor Inc.
ZL30226/7/8
2.2.1 TX Cell RAM and TX FIFO Length
Data Sheet
The internal TX Cell RAM can hold up to 128 cells. The following 10 cells are reserved for ZL30226/7/8 operation: * * * one ICP cell for each IMA Group for a total of eight cells one common Filler Cell used in IMA mode one Idle Cell used in TC mode
The remaining 118 cells can be assigned to any of the 40 TX FIFOs. The TX FIFOs are divided into 24 TX UTOPIA FIFOs and 16 TX Link FIFOs. The ZL30226/7/8 implements one TX UTOPIA FIFO for each link when used in TC mode and one for each IMA Group, totalling up to 24 TX UTOPIA FIFOs. Each TX UTOPIA FIFO is associated with one TX UTOPIA Address. Please refer to section 5.0 "UTOPIA Interface Operation" for more details. In addition, for each link to be used in IMA mode, an internal TX Link FIFO is utilized. These TX Link FIFOs hold the cell streams that are to be sent on each TX serial port. There is a total of 16 TX Link FIFOs and their size is programmed on a per group basis using the TX IMA Control (0x0321-0x0324) register. When a link is used in TC mode, its corresponding TX Link FIFO is disabled and the TX Link UTOPIA FIFO is used. The ZL30226 and ZL30227 support a subset of the 16 links and only the registers corresponding to available links are meaningful. TX IMA UTOPIA FIFO Length Definition (0x0093-0x0096) registers are used to set the size of the IMA FIFO. A maximum of 6 cells can be assigned to any single FIFO. The size of unused TX IMA UTOPIA FIFOs should be set to zero. The recommended size for the IMA Group TX UTOPIA FIFO is 2. In IMA Mode, the ATM User Cells are first placed in the TX IMA UTOPIA FIFO and then transferred, by the internal round robin scheduler, to the proper TX Link FIFO. The TX IMA Control (0x0321-0x0324) registers are used to set the size of the internal TX Link FIFO for a link in IMA mode. An upper and lower level limit must be set for the internal TX Link FIFO. The recommended upper limit value for the internal TX Link FIFO is five and the recommended lower limit is one when operating in ITC clocking mode. When operating in CTC mode, the recommended upper limit value for the internal TX Link FIFO is six and the recommended lower limit is one. In the case where CTC mode is used and when the ICP cells on all the links are sent with the same ICP cell offset and when carrying a CBR-type traffic, an upper value of 7 may be required. In TC Mode, the ATM User Cells are queued in the TX Link UTOPIA FIFO (0x008B - 0x0092) until sent over the serial link.
2.3
Parallel to Serial TDM Interface
The TDM TX Link Control Register (0x0600-0x060F) and TDM RX Link Control Register (0x0700-0x070F) registers are used to select the serial mode of operation. Additionally, the serial links can operate at rates up to 2.5 Mb/s individually, or up to 5.0 Mb/s when paired or 10 Mb/s when grouped in fours. Refer to Description of the TDM interface for more details.
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2.4 ATM Transmit Path in IMA Mode
Data Sheet
The ZL30226/7/8 supports up to eight independent IMA Groups. Each of the available serial links can be assigned to any one of these IMA Groups. A serial link cannot be assigned to more than one IMA Group. Refer to Figure 5 for a functional block diagram of the transmitter. The IMA transmitter splits the incoming stream into N sub-streams, where 1 N (maximum available serial links). Each sub-stream is passed to a separate line interface device that transmits the cells on a physical link. The physical line rate is any serial rate up to 2.5 Mb/s (Serial Mode). The transmitter inserts ICP cells in the various outgoing streams according to the IMA specification. The ICP cells are inserted every M ATM cells on each link and is the task of the scheduler.
2.4.1
IMA Frame Length (M)
The IMA frame length (value of M) can be 256, 128, 64, or 32. The value of M for each IMA Group is set by the TX IMA Group FIFO Length Definition (0x0093-0x0096) registers. M is fixed once an IMA Group is setup and should remain unchanged as long as that group is operational.
2.4.2
Position of the ICP Cell in the IMA Frame
The TX ICP Cell Offset (0x0310-0x0317) registers control the position of the ICP cell in the IMA frame for each link. This parameter should remain unchanged as long as that group is operational.
2.4.3
Transmit Clock Operation
The ZL30226/7/8 supports both the Common Transmit Clock (CTC) and Independent Transmit Clock (ITC) modes of operation. The desired mode is specified by writing to the TX Group Control Mode (0x0300-0x0307) register. A reference link must be specified in the TX Group Control Mode (0x0300-0x0307) register. The ZL30226/7/8 introduces a Stuff cell on the reference link every 2048 cells and determines the appropriate time to insert a Stuff cell on the remaining group links. See paragraph 2.4.4, Stuff Cell Rate, for more details. The clocking mode and reference link are fixed once an IMA Group is set up and should remain unchanged as long as that group is operational. The reference link should not change unless problems are reported with the link.
2.4.4
Stuff Cell Rate
The Stuff event algorithm differs between CTC and ITC modes. In CTC mode, the Stuff event is typically fixed and appears in the same IMA frame on all IMA Group links. In ITC mode, the Stuff event is determined using an adaptive algorithm that relates the level of the internal TX Link FIFO to that of the TX link FIFO of the Reference link. The ZL30226/7/8 implements 2 different stuffing algorithms: a fixed stuffing rate and an adaptive stuffing rate. The Stuffing events do not happen more frequently than once every five IMA frames. TX Group Control Mode (0x0300-0x0307) register bit 4 selects either the adaptive or fixed algorithm. Bit 5 determines the timing mode declared in the ICP cell. There are three possible combinations: * * * CTC Mode with internal Fixed algorithm CTC Mode with internal Adaptive algorithm ITC Mode with internal Adaptive algorithm
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Data Sheet
In CTC mode, when using the Fixed algorithm, the Stuff event is periodic and will appear in the same IMA frame, once every 2048 cells, on each link that is part of the IMA Group. In CTC mode, when using the Adaptive algorithm, the Stuff event will occur at an average rate of once every 2048 cells on each link and may not occur in the same IMA Frame on all the links. The reference link has one Stuff event every 2048 cells. In ITC mode, the Stuff event is determined using the adaptive algorithm that relates the level of the internal TX Link FIFO with that of the TX Link FIFO of the Reference link. The reference link has one Stuff event every 2048 cells. The state of bits 7 and 15 in the TX IMA Control (0x0321-0x0324) register determines whether a Stuff indication is generated in the first or first four frames preceding a Stuff event.
2.4.5
IMA Data Cell Rate
The ZL30226/7/8 computes the internal TX IMA Data Cell Rate (IDCR) for each IMA Group. The cell rate for the IMA Group reference link, specified in the TX Group Control Mode (0x0300-0x0307) register, is integrated over a programmable period of time. The integration period is programmed in the TX IDCR Integration register and the value for T1 or E1 services is indicated in Table 1.
TDM Mode SHDSL (T1 24 channels) SHDSL (E1 30 channels)
Preferred Value TX IDCR Integration register (50 MHz) 219 clocks 220 clocks
Table 1 - IDCR Integration Register Value Alternately, the integration period can be determined using the following equation:
NumberofCells(perperiod) = [CellRate(persecond)] [IntegrationPeriod(insecond)]
The optimum performance will be reached when selecting an integration period which results in a number of cells per integration period which is close to an integer number of cells. As example, for a cell rate equivalent to E1 service (30 timeslots per frame with a frame rate of 8 KHz).
NumberofCells = 94.97 = [30bytes ! 8KHz/(53bytespercells)] [(220) ! 1/(50MHz)]
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Zarlink Semiconductor Inc.
ZL30226/7/8
2.4.6 IMA Controller (RoundRobin Scheduler)
Data Sheet
The IMA controller produces the cell stream to be sent to the TDM blocks using the following four cell types: * * * * Data cells received from the UTOPIA port (User cells) Filler cells IMA ICP cells with Link status information Stuff cells
At an IDCR clock tick, the RoundRobin scheduler inserts either an ICP cell, a User cell or a Filler cell into the TX Link FIFO of the next link of the IMA group, based on ascending link ID numbers. An ICP cell is inserted every M cells and a stuff event is inserted when indicated by the stuffing algorithm. If it is not time for an ICP cell and if the traffic is not enabled for the link, then a Filler cell is inserted in the TX Link FIFO. If the traffic is enabled and there is a User cell in the TX IMA Utopia FIFO, then the User cell is transferred from the TX IMA UTOPIA FIFO to the TX Link FIFO. If there is no User cell in the TX IMA UTOPIA FIFO, then a Filler cell is inserted in the TX Link FIFO. Byte 1-5 6 7 8 9 10 11 12 13 14 15 16 17 18-49 50 51 52-53 Description ICP Cell Header OAM label Cell ID, Link ID IMA Frame Sequence ICP Cell Offset Link Stuff Indication Status Change Indic. IMA ID Group Status and Control Sync. Info. Test Control TX Test Pattern RX Test Pattern Link Status and Control Unused End-to-End Channel CRC Error Control S/W control Hardware Control. The Link ID is programmed by S/W via other registers. Hardware Control H/W Control (Programmed by S/W through other registers) H/W Control (Programmed by S/W through other registers) H/W Control S/W Control S/W Control except for value of M H/W Control (Programmed by S/W through other registers) S/W Control S/W Control S/W Control S/W Control S/W Control S/W Control H/W Calculation Table 2 - ICP Cell Description Control Source Content of Header is under S/W control. The HEC is calculated by H/W.
2.4.7
ICP Cell Generator
Once per IMA frame, an ICP cell is transmitted on each link of the IMA Group. The content of the ICP cell is controlled both by ZL30226/7/8 and software. The software content of the ICP cell bytes is stored in buffer RAM. A copy of the ICP cell for each group is kept in the internal Transmitter Cell RAM. The ICP cell to be transmitted on each link is assembled on an as required basis under the control of the internal RoundRobin scheduler and ICP Cell Modifier.
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Zarlink Semiconductor Inc.
ZL30226/7/8
Hardware controls the following bytes of the ICP cell: * * Byte 5 - the HEC is always calculated and inserted by the ZL30226/7/8
Data Sheet
Byte 6 - the TX OAM Label is defined by the software and the value contained in this location is transmitted in all ICP cells, Stuff Cells and Filler cells sent on all the links that are part of the corresponding TX IMA group Byte 7 - the TX Link ID (0x0336 - 0x033D) registers are used to set the Link Logical ID and the cell type is determined by the internal controller on a per link basis Byte 8 - the frame sequence number is controlled by an internal counter Byte 9 - the TX ICP Cell Offset (0x0310-0x0317) registers are used to set this value and is inserted on a per link basis Byte 10 - the link Stuff indication is inserted automatically and the advance indication option is programmed by the TX IMA Control (0x0321-0x0324) registers on a per link basis Byte 11 - the SCCI is controlled by internal circuitry. The SCCI is incremented by one for each transfer of the TX ICP cell from the buffer area to the TX Cell RAM. Byte 13 - the value of M is programmed through the TX Group Control Mode (0x0300-0x0307) register Byte 14 - the TX Group Control Mode (0x0300-0x0307) register is used to set the Transmit Timing Information and define the reference link Bytes 52 and 53 - the calculated CRC-10 Error Control bits are inserted automatically
* * * * * * * *
Software controls all remaining bytes of the ICP cells. It also maintains and updates all bytes that are not directly controlled by the ZL30226/7/8. A dedicated address is reserved for each ICP cell byte for each of the eight IMA Groups. This permits direct access to any of the bytes stored in each of the eight ICP Cell registers. Refer to Table 2, ICP Cell Description, for details on the ICP cell byte contents. To avoid updating or corruption problems, the internal copy of the ICP Cell cannot be directly accessed. ICP cells are prepared in a buffer area (RAM inside the ZL30226/7/8) and transfer commands are issued to copy the content of the ICP cell into the internal Cell RAM area and to start using this new ICP cell. The ZL30226/7/8 uses a flag (status bit) to indicate that this transfer is underway. Changes should not be made to the content of the ICP cell in the buffer area until the transfer to the internal memory is complete. The status bit is cleared during the transfer and returns to'1' on completion of the transfer. IMA Groups are controlled independently. When access to the ICP cell of one group is prohibited, the other ICP cell buffer areas can still be updated. The TX ICP Cell Handler (0x0086) and TX ICP Cell Interrupt Enable (0x0088) registers are used to initiate a transfer and enable an optional interrupt to indicate when the process is complete. The SCCI field is incremented by one for each transfer command performed which includes a change in at least one byte of the ICP cell.
2.4.8
IMA Frame Programmable Interrupt
An optional interrupt is provided at the end of an IMA frame to simplify software implemented changes in the Group Control and Status field. This interrupt can be enabled on an as required and per group basis to implement a frame counter. The TX IMA Frame Indication (0x0087) and TX IMA Frame Interrupt Enable (0x0089) registers are used for the end of frame indication and frame interrupt.
2.4.9
Filler Cell Definition
The content of the Filler cell is pre-initialized and conforms with the IMA Specification. The OAM label in the Filler Cell is copied from the ICP cell, allowing both IMA 1.0 and IMA 1.1 to run simultaneously on the same device.
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Zarlink Semiconductor Inc.
ZL30226/7/8
2.4.10 TX IMA Group Start-Up
Data Sheet
Initialize the TX IMA Group start-up as follows: (Note: The startup procedure below is given indicating the most important steps. A more detailed and complete sequence can be found in the Zarlink IMA Core Software). For ZL30226 only groups 0, 1, 2 and 3 are used. * * * Configure the TX TDM port(s) by writing to the TDM TX Link Control (0x0600-0x060F) registers. Write the value of M, the Timing Mode and the reference link number to the TX Group Control Mode (0x0300-0x0307) register corresponding to the IMA Group number to be initialized. Write the Link ID (LID is between 0-31) to TX Link ID (0x0336-0x033D) registers for each link to be used in the IMA Group. LID should not be changed when a group is operational. Ensure each link that is part of an IMA group has a unique LID (note that the ZL30226/7/8 does not verify LIDs). Write the ICP Cell Offset value to TX ICP Cell Offset (0x0310-0x0317) registers. This value depends on the value of M. Typically, the reference link will have a delay of 0 cells in the IMA Frame and the ICP cell in each other link will be evenly spaced in a multiple of M/N cells (where M is defined in the IMA specification and N is the number of links). The offset value for an operational group should not be changed. Write to the TX Link Control (0x0318-0x031F) registers to put the link(s) in IMA mode and to enable the transfer of ATM User Cells when required.
*
*
2.4.11
TX Link Addition
The ZL30226/7/8 supports software controlled link addition to an existing IMA group. Link addition is used to increase the available bandwidth. The TX Link Control registers (0x0318-0x031F), the TX Link ID (0x0336-0x033D) and TX ICP Cell Offset (0x0310-0x0317) registers are initialized first with the proper IMA Group information. The link is assigned to a TX IMA group by writing to bits 10:8 or bits 2:0 of the TX Link Control (0x0318-0x031F) register. Before the TX link can be configured in IMA mode, the value of 0x108 + group number has to be written in the TX Add Link Control Register (0x0333). The link is then configured in IMA mode by writing to the bit 3 or 11 of the TX Link Control (0x0318-0x031F) register. The TX IMA Mode Status (0x0346) register is monitored to detect when the link is reported in IMA mode. TX Link control (0x0318-0x031F) register bit 6 or 14 determines when ATM User cells can be sent. Last, the TX Add Link Control Register (0x0333) is written with 0x0100
2.4.12
TX Link Deletion
There are two reasons to remove a link: the required bandwidth decreases or a link becomes faulty. The ZL30226/7/8 supports link deactivation under software control. A link stops transmitting User cells when bit 6 or 14 of the TX Link Control register (0x0318-0x031F) is set to 0. Filler and ICP cells will still be sent on the link. The link is removed from an IMA group by first setting bit 3 or 11 of the TX Link Control register (0x0318-0x031F) to 1 while keeping the original IMA group number. The IMA group number can be changed only when the link is in TC mode as reported in the TX IMA Mode Status register (0x0346). It then can be assigned to another IMA group. When removing the last link of a TX IMA group, the TX UTOPIA FIFO has to be empty. This can easily be done by first disabling the source of ATM cells (ATM Utopia controller), then disabling the TX IMA UTOPIA Port using the UTOPIA Input Link PHY Enable (0x0050) or UTOPIA Input Group PHY Enable (0x0051) registers while still keeping the "Send User Cell" bit of the TX Link Control (0x0318-0x031F) register set to 1. The above procedure can then be applied to assign the link in TC mode. When the link is configured in TC mode, IDLE cells are transmitted. Writing to the TDM TX Link Control (0x0600-0x060F) registers either turns off the transmitter or reconfigures the link into another mode.
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Zarlink Semiconductor Inc.
ZL30226/7/8
Transmitter Cell RAM Cell_In_Control Tx Link UTOPIA FIFO[N] P/S
Data Sheet
ATM In
Serial Streams Link [N]
Output Controller and Cell Distribution
Figure 6 - Functional Block Diagram of the Transmitter in TC Mode
2.5
ATM Transmit Path in TC Mode
A maximum of sixteen independent serial interfaces can be configured in TC mode (16 for the ZL30228, 8 for the ZL30227 and 4 for the ZL30226). Figure 6 gives a functional block diagram of the transmitter in Transmission Convergence (TC) mode. ATM cells received from the ATM port are placed in a TX Link UTOPIA FIFO, waiting to be transmitted. If the Idle/Unassigned cell removal option is selected, these cells are dropped. If the TX LINK UTOPIA FIFO is empty, an Idle cell is sent to the output link. The content of the Idle cell is pre-initialized with the header bytes set at 0x00, 0x00, 0x00 and 0x01. The payload bytes are set to 0x6A. TX LINK FIFO Length Definition (0x008B-0x0092) registers are used to set the TX Link UTOPIA FIFO size. The total number of cells in all the TX Link UTOPIA FIFOs, TX IMA UTOPIA FIFO and TX Link FIFO (includes the links used in IMA Mode and the links used in TC Mode) is limited to 118. Idle Cells are transmitted on the TC serial interface until the bit corresponding to the link in the UTOPIA Input Link PHY Enable (0x0050) register is set. Then, the ATM User cells are transferred from the Input UTOPIA port to the TX serial port.
3.0
The ATM Receive Path
The receive path corresponds to the cell flow from the PHY (serial TDM) interfaces to the ATM UTOPIA Interface. The ZL30226/7/8 provides cell delineation and optional cell filtering to discard Unassigned or Idle cells on each link. The incoming cells are stored in the external RAM, required in IMA mode, to perform cell recovery due to delay variation between the links introduced by the network.
3.1
Cell Delineation Function
This block provides the circuitry necessary to perform functions such as Cell Delineation (CD), cell payload de-scrambling, HEC verification and filtering of Idle (non-IMA) cells. The CD circuit delineates ATM cells received from the payload of the T1, E1,J1 or DSL frame through the flexible TDM Interface. When performing delineation, valid HEC calculations are interpreted to indicate cell boundaries. The CD circuit performs a sequential hunt for a correct HEC sequence. While performing this hunt, the cell delineation state machine is in the HUNT state. Figure 7 depicts a state diagram of the cell delineation operation.
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Zarlink Semiconductor Inc.
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Valid HEC (byte by byte) Incorrect HEC (cell by cell)
Data Sheet
.
HUNT ALPHA Consecutive Incorrect HEC (cell by cell)
PRESYNC
SYNC
DELTA Consecutive Correct HEC (cell by cell)
Figure 7 - Cell Delineation State Diagram When a valid HEC is found, the CD circuit locks on the cell boundary and enters the PRESYNC state. The PRESYNC state keeps checking the HEC to ensure that the previous indication was not false. False indications are interpreted to mean the circuit is not tracking valid ATM cells. After entering the PRESYNC state, the first false indication triggers a transition back to HUNT state. If the PRESYNC state HEC is correct, then a transition to the SYNC state occurs after "" cells (DELTA in ITU I.432) are correctly received. In the SYNC state, the CD circuit treats the incoming ATM cell stream as stable and the ZL30226/7/8 functions normally. While in the SYNC state, if an incorrect HEC is obtained "" consecutive times (ALPHA in ITU I.432), cell delineation is considered lost and a transition is made back to the HUNT state (see Figure 7). As defined by the ITU I.432 recommendations, the value of ALPHA and DELTA determine the robustness of the delineation method. The value of ALPHA and DELTA for the Cell Delineation state machine are defined in the Cell Delineation (0x00C9) register. Only one set of values is defined for the sixteen Cell Delineation state machines. The status of the CD state machine for each link is available in bits 0 through 15 of the Cell Delineation Status (0x00E6) register. The ITU I.432 suggested values are: ALPHA = 7; and DELTA = 6. Loss of Cell Delineation (LCD) is detected by counting the number of incorrect cells while in HUNT state. The ZL30226/7/8 provides an internal Loss of Delineation (0x00C8) register to set the threshold for this count. The LCD state for each link is available in bit 1 of the IRQ Link Status (0x0435 - 0x4444) registers, and in bit 6 of the RX Link ID Number (0x00E3) register. The LCD and End of LCD status bit reports the current condition of the Cell Delineation State Machine at the time it is read, and can optionally generate an interrupt (IRQ). Table 3 provides the time, in microseconds, for the CD circuit to receive a full ATM cell from the SHDSL emulating T1 payload and SHDSL emulating E1 payloads. Format SHDSL T1 SHDSL E1 Average Cell Time (s) 276 221
Table 3 - Cell Acquisition Time While the cell delineation state machine is in the SYNC state, the verification circuit implements the state machine shown in Figure 8.
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Zarlink Semiconductor Inc.
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Data Sheet
DELTA Consecutive Correct HCS's (PRESYNC State)
Cell Accepted
ATM CELL DELINEATION SYNC STATE
HCS Multi-Bit Error Detected (cell discarded)
Cell Discarded
ALPHA Consecutive Incorrect HCS's Jump to HUNT State
HCS Single Bit Error Detected (corrected or dropped) Correction No HCS Errors Detected Detection
Figure 8 - SYNC State Block Diagram In normal operation, the HEC verification state machine remains in the 'correction' state. Incoming cells containing no HEC errors are passed to the receive IMA block (RX IMA). Incoming single-bit errors can be corrected if required by the application (i.e., single bit error correction can be enabled or disabled). After correction (when enabled), the resulting ATM cell is passed to the ICP Processor block for IMA sequencing control (IMA mode) or Rx Link UTOPIA FIFO (TC mode). If a single or multi bit error occurs, the state machine transitions to the 'detection' state. When a cell with a good HEC is detected, the state machine returns to the 'correction' state. The HEC calculation normally includes the ATM FORUM polynomial (X6 + X4 + X2 + 1). The use of the polynomial can be disabled by writing to bit 1 or 9 of the RX Link Control (0x00C0-0x00C7) register.
3.2
De-Scrambling and ATM Cell Filtering
The CD circuit can de-scramble the cell payload field. The de-scrambling algorithm can be enabled or disabled using bit 5 or 13 of the RX Link Control (0x00C0-0x00C7) registers. The ZL30226/7/8 can be programmed, using the RX Link Control (0x00C0-0x00C7) registers, to discard received ATM cells with HEC errors using bits 2 and 10. HEC error correction is optional and can be enabled by the CPU. When the option to correct an incoming HEC value with 1 bit error is selected, the HEC is corrected and the cell is not counted as a cell with a bad HEC. If the option to remove the cells that are received with a bad HEC is selected, then the incoming cells are replaced by a Filler cell (in IMA mode) or discarded (in TC mode). The counter is not incremented if the HEC value is corrected, when the option is enabled. Incoming Idle and Unassigned cells can be detected and dropped automatically.
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RAM Area
Data Sheet
RXCK S/P DSTi [0]
Cell Delin.
ICP Proc.
IMA Frame State Machine
UTOPIA Interface
RAM Controller
RX Scheduler
RXCK S/P DSTi [15]
Cell Delin.
ICP Proc.
IMA Frame State Machine
Link Info Registers
RX Cell Buffer
Rate Recovery
Recovered Cell CLK
TDM Ring Control
From TX Block
Micro
To TDM Ring
Figure 9 - ZL30228 Receiver Circuit in IMA Mode
3.3
ATM Receive Path in IMA Mode
The block diagram in Figure 9 illustrates the ZL30228 IMA mode receive path. The receiver must rearrange the incoming bit streams from up to 16 links into a single UTOPIA cell stream.
3.3.1
ICP Cell Processor
In IMA mode, the transmitter inserts special ICP cells in the various outgoing streams every M ATM cells to comply with the IMA specification. The receive block uses these ICP cells to synchronize with the Far End transmit side and to reconstruct the original ATM cell sequence.
3.3.2
IMA Frame Synchronization
The ZL30226/7/8 implements IMA Frame Synchronization State Machines (IFSM) for each link, as described in Section 11 of the IMA Specification. The values of Alpha, Beta and Gamma are programmable through the IMA Frame Delineation (0x00CA) register. Their values are the same for all links. After the link is programmed to be in IMA mode by writing to the RX Link Control (0x00C0-0x00C7) register, the IMA Frame State Machine is enabled. At the same time, the parameter's values of the RX link are latched in internal reference registers and are used to determine whether the received ICP cell meets the valid ICP cell criteria to determine IMA frame synchronization.
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Data Sheet
Incoming ICP cells are automatically detected by the ICP Processing block. As soon as one valid ICP cell is received, the IMA Frame State Machine moves to the IMA PRESYNC state. When Gamma-valid ICP cells are received, the state machine moves to the IMA SYNC state. In the IMA PRESYNC state, one errored or missing ICP cell causes the state machine to return to the IMA HUNT state. In the IMA SYNC state, the state machine transitions to the IMA HUNT state by any of the following events: * * * one missing ICP cell Alpha consecutive invalid ICP cells Beta consecutive errored ICP cells
After the received information is validated, the IMA Group is configured by writing to the RX Reference Link Control (0x0209 - 0x0210), the RX Link Control (0x00C0-0x00C7) and RX Recombiner (0x0201 - 0x0208) registers. Bits 3 and 2 of the RX State (0x00E4) register report the IMA Frame State Machine state for a selected link. When in IMA HUNT mode, the information required to perform the verification is extracted from the ICP cells received. The IMA Frame State Machine Status (0x00E5) indicates whether a link's IFSM is in a Synchronized State. Each link has one corresponding bit in this register.
3.3.3
Link Information
All required link information for verification and link validation is extracted from the received ICP cells. The IMA ID, Link ID (LID), Reference Link Number, ICP Cell Offset and Frame Length can be read and validated before enabling an IMA Group link. Software obtains this information by writing to the RX Load Values (0x00DC) register to select a link and then reading the RX Link IMA ID (0x00DE), RX ICP Cell Offset (0x00DF) and RX State (0x00E4) registers. This information can also be obtained by collecting all the received ICP cells in the RX ICP Cell Buffer and then processing the contents of the ICP cell (i.e., writing to the RX Cell Type RAM (0x0100 and 0x0101) register and then reading from the RX ICP cell buffer). The contents of the link information registers should be read and validated after enabling the RX TDM link in the RX Link Control (0x00C0-0x00C7) register and before enabling the IMA mode. The link information can be accessed when a link is either in TC or IMA mode (but will not be updated in IMA mode).
3.3.4
RX OAM Label
The RX OAM Label is treated differently than the other link's parameters. Four User Defined OAM Label (0x00CC-0x00CF) registers (1 register per 2 RX IMA Groups) are used to defined the RX OAM Label. Its value is written by the software and can be changed at any point in time. However, the RX OAM Label has to match the value contained in the RX ICP cell for the IMA Frame State Machine to reach the ACTIVE state.
3.3.5
Out of IMA Frame (OIF) Condition
Status bits in the RX OIF Status (0x00D9) register, one bit per link, report OIF conditions. The status bit latches an OIF condition which corresponds to a transition of the IFSM from SYNC to HUNT. The OIF condition is reported as a status bit only and cannot generate an interrupt. The status bit is cleared by writing a 0 to the corresponding bit. There are 16 OIF counters, one per link. For each OIF transition, the 8-bit counter associated with the link is incremented by one. The counter can be read with indirect access when issuing a load command with the RX Load Values (0x00DC) register. The counter can be cleared by writing to the RX OIF Counter Clear Command (0x00DA) register.
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3.3.6 Loss of IMA Frame (LIF) Synchronization
Data Sheet
A link is declared out of IMA Frame (LIF) synchronization state when the IFSM goes in HUNT mode for 'gamma +2' frames after it was in SYNC state. Loss of IMA Frame (LIF) and end of LIF can optionally generate an interrupt (IRQ). This condition is latched in bits 2 and 10 of the IRQ Link Status (0x0435-0x0444) registers. Refer to section 6.2.2 IRQ Link Status and IRQ Link Enable Registers for more details. The LIF status bit reports the current condition of the IMA Frame State Machine at the time it is read.
3.3.7
Filler Cell Handling
The ZL30226/7/8 scans each incoming cell received for the Filler Cell Indication code. Filler cells are written to external RAM to keep the IMA frame aligned. They are automatically discarded after being read from the external RAM by the recombiner.
3.3.8
Stuff Cell Handling
Each incoming ICP cell received is scanned for the Stuff Indication Code. Stuff cells are inserted at the transmit end as two identical and consecutive ICP cells with the Link Stuff Indication Bits set as defined in the IMA specification. The ZL30226/7/8 automatically discards one of the two Stuff cells without storing it in external RAM. The other is kept and processed as a regular ICP cell. IMA Frame synchronization is maintained for all cases (except case 7, O-19 optional requirements) as described in Figure 20 of the IMA Specification.
3.3.9
Received ICP Cell Buffer
An internal buffer is implemented to collect cells from the RX TDM links for analysis by the software. This storage unit has a circular buffer for each link and contains up to three cells per link. The buffer can selectively collect: * * * * all valid cells received on a RX TDM port all valid ICP cells all valid ICP cells which contain new information (as indicated by the SCCI field, valid only when the link is in IMA mode) no cells
The type of cells collected is defined in the RX Cell Type RAM (0x0100 and 0x0101) registers. A status bit and a maskable IRQ alerts the software when a new cell is waiting for processing in a specific link. These are found in the IRQ Link Status (0x0435-0x0444) and Enable (0x0445-0x0454) registers. Software can directly access the cells in the RX buffer through a two-cell-wide access window using RX IMA ICP Cell (0x0800 - 0x0BFF). This access window can be advanced, one cell at a time, by issuing a command to move the internal pointer to the next cell. Since the window accesses two cells, the last processed cell can be accessed at the window's base address and the new cell at the base address plus 0x20. The RX Cell Level FIFO Status (0x0106) register is used to read the level of any of the 16 RX ICP Cell buffers. A '0' in this register signifies that no new cell has been received. A '2' indicates the possibility that one or more cells have been missed (overflow condition). The cell in the last entry of the circular buffer is a temporary buffer (scratch pad). If, for example, the Cell FIFO level is 2, it is constantly overwritten by any new valid incoming cell. When the level is 0, the cell that is at the window's base address is never overwritten as is kept for reference. The RX Cell Buffer Increment Read Pointer (0x0105) register is used to advance the access window by 1 cell at a time. Upon the command, the Buffer level is decreased by 1. When the level reaches 0, the window is not advanced anymore.
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Data Sheet
During the start-up phase, the software can choose to collect all valid ICP cells from a RX TDM port and determine if the parameters are acceptable to proceed to start-up an IMA group. In normal IMA operating mode, the software will choose to collect only valid ICP cells with changes. The Status and Control Change Indication (SCCI) is monitored for all valid ICP cells received. If the SCCI field indicates a change in the ICP cells, they are put aside for processing by software. To accelerate the processing of ICP cells that contain changes, any byte of the last and next processed ICP cell can be accessed directly. To reduce the total processing time by the software, only those bytes that need to be read are accessed. The storage unit keeps the last read ICP cell and has room for up to three new ICP cells.
3.3.10
Rate Recovery
The ZL30226/7/8 computes the internal RX IMA Data Cell Rate (IDCR) for each IMA Group. The cell rate of the reference link is integrated over a programmable period of time. Software must specify the reference link for the IMA Group in the RX Reference Link Control (0x0209 - 0x0210) registers and the period of integration in the RX IDCR Integration (0x0219 - 0x021C) registers. Refer to TX IMA Data Cell Rate in Section 2.4.5. The Rx Preprocessor is also available to aid the comparison of cells. See section 6.4. As an option, the number of the link to be used as a reference link can be extracted automatically from octet 14 of the received ICP cell. This option is selected by bit 4 of the RX Reference Link Control (0x0209 - 0x0210) registers.
3.3.11
Cell Buffer/RAM Controller
The received cells are temporarily stored in external memory buffers until they can be correctly re-ordered for output. Memory size depends on the number of links and the maximum delay allowed between the links. The memory requirements for different configurations are listed in Table 4: The memory is organized in blocks of 64 bytes. Each block can hold one cell. The following equation can be used to determine the maximum delay value or the required RAM size for a determined delay:
[RAMsize] 64 1 (16)
MaxDelay =
[1 CellTime]
To simplify the RAM interface and pin loading, the ZL30226/7/8 supports the following six, register selectable, external memory configurations: * * * * * * one 32 KByte SRAM device two 32 KByte SRAM devices one 128 KByte SRAM device two 128 KByte SRAM devices one 512 KBytes SRAM device two 512 KBytes SRAM devices.
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Delay (msec) Memory Size (Kbytes) 32 Kb 64 Kb 128 Kb 256 Kb 512 Kb 1024 Kb T1 rate (1.5 Mbit/s) 8 16 34 69 140 281 E1 rate (2 Mbit/s) 6 13 27 55 112 225
Data Sheet
Note: Assuming a Guardband of 4 cells
Table 4 - Differential Delay for Various Memory Configuration
3.3.12
Cell Sequence Recovery
When an IMA Group is active, the IMA recombiner manages the pointers to the external RAM write and read location for the stored ATM cells. A cell is read out from the buffer located in the external RAM corresponding to the lowest link ID (LID) of the IMA Group and placed in the RX IMA UTOPIA FIFO. After a complete cell read, a read pointer is set to the buffer corresponding to the next LID. At the following IDCR clock cycle, the next available cell is read. ICP cells are skipped and Filler cells are discarded. This operation is done in a RoundRobin fashion based on the LID value for each IMA Group link. Faulty conditions (i.e., buffer overflow, excessive delay) are reported through the IRQ Link Status (0x0435-0x0444) and IRQ IMA Overflow Status (0x0420-0x0427) registers.
3.3.13
Delay Between Links
The delay values between links reflect the various transit delays though the network. In order to rebuild the original ATM cell sequence, the link that exhibits less transport delay has to be stored until the data from the slowest link (the link having the largest transport delay) has arrived. The link that exhibits the largest transport delay will be the link that requires the least cells to be stored. Conversely, the line that exhibits the least transport delay is the link that requires the largest number of cells to be stored. As a network parameter, the delay on a link should be constant. The delay between links should only change when links are replaced, added to a group (introducing a new greatest or least delay link) or removed from a group (removing a greatest or least delay link). Indirect access is provided to internal registers which hold the various link delay values. The link number and delay type are first selected by writing to the RX Delay Select (0x02AA) register. After 2 system clock cycles, the 11-bit value in the RX Delay (0x0285) and the RX Delay Link Number (0x0286) registers are updated and can be read. The valid delay types are: the Maximum Delay over Time, the Current Maximum Delay and the Current Minimum Delay for an IMA group and the Current Delay values for any link.
3.3.13.1
RX Recombiner Delay Value
The ICP Cell from each link of the same IMA Group is used to determine the external SRAM read and write pointers. The distance between the read and write pointers is referred to as the recombiner delay. Setting the recombiner delay to the maximum acceptable delay results in a fixed recombiner delay that is not optimum. For example, setting recombiner delay to 25 msec when the worst case delay is 12 msec results in an additional, unnecessary delay of 13 msec. The minimum recombiner delay would be the current worst case differential delay. In the example above, the recombiner delay would be set to 12 msec. In this case, a link with larger transport delay than the current worst value cannot be added to an existing IMA group: the cells from this slower link have not arrived when the cells
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Data Sheet
sequence is rebuilt, as the read pointer was set using the previous worst case link. If this slower link is to be added, then the recombiner process has to stop for the time required to receive the cells on the slower link and then the recombiner process can resume. This causes disruption in the operation of the recombiner and will affect the Cell Delay Variation (CDV). To provide an optimal recombiner delay, the ZL30226/7/8 adds a guardband delay to the current worst case recombination delay when the IMA Group is first started up. Guardband delay is programmable and minimizes the number of disruptions that would otherwise occur in accommodating link delays exceeding the current worst case. The guardband delay value is specified for each IMA group by writing to the RX Guardband/Delta Delay (0x0287-0x028E) registers. It should be the smallest value possible consistent with minimizing the disruptions (the smallest allowed value is 4). When operational, the value of the guardband delay corresponds to the delay value of the link having the greater transport delay (the link where the data is the last to arrive to the ZL30226/7/8).
3.3.13.2
RX Maximum Operational Delay Value
The various delays on links of the same IMA Group are measured and compared to the programmed 'maximum allowable value' stored in the RX Maximum Operational Delay (0x029A-0x02A1) registers for the IMA Group. This value corresponds to the worst delay value that is expected. This value cannot be larger than the number of cells that can be stored in the external memory. The smallest 'maximum allowable value' is four cells. These values are independently established for each of the four IMA Groups.
3.3.13.3
Link Out of Delay Synchronization (LODS)
If a link to be added is slower and cannot be accommodated by the present guardband, an LODS signal is generated and the link delay value is reported negative. The value reported is with respect to the read pointer and represents the minimum number of cells that has to be added to the present guardband before adding the link in the IMA group. See paragraph 3.3.13.6 Incrementing/Decrementing the Recombiner Delay for more details. If a link to be added is faster and would cause its write pointer to be set beyond the RX Maximum Operational Delay (0x029A-0x02A1) programmed value, then the link is reported to be faulty through an LODS condition. The recombination process will not be affected as long as the amount of delay is not larger than the total number of cells in the external memory. LODS will also be reported if, during operation, the delay of a link changes to exhibit higher or lower delay resulting in a negative delay value or a value beyond the RX Maximum Operating Delay value. LODS events are reported by the IRQ Link Status (0x0435) register and investigated by selecting the current maximum delay using the RX Delay Select (0x02AA), RX Delay Register (0x0285) and RX Delay Link Number (0x0286) register. Link Out of Delay Sychronization (LODS) and end of LODS can optionally generate an interrupt (IRQ).
3.3.13.4
Negative Delay Values
If the recombiner process is enabled for a link that exhibits a negative delay value, then the recombiner process will be suspended until the write pointers are moved in such a way that the delay is reported with a positive value of 4. The recombiner process will then resume and no cells will be lost. The same behavior applies if the delay value of a link which is part of the round robin process (recombiner bit ON) becomes negative: the recombiner process will be suspended until the delay value becomes positive with a value of 4. The latter condition can happen under severe error conditions if the recombiner process of the faulty link is not disabled.
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3.3.13.5 Measured Delay Between Links
Data Sheet
The values and delay type for a selected link(s) or IMA Group can be read using the RX Delay Select (0x02AA) register. IMA Group delay types include: the Maximum Delay over time; the Current Maximum Delay and the Current Minimum Delay of an IMA Group. Current Link Delay reports the Current Delay of a link. These values are all reported through a common RX Delay (0x0285) register. The value is in number of cells. All delay values include the guardband delay value. The RX Delay Link Number (0x0286) register reports the link number associated with the delay value that is currently in the RX Delay (0x0285) register, with the exception for the Maximum Delay over time value, where the link number reported is not valid (reports value of 0). The Maximum Delay over time value can be reset at any time by writing a clear command to bit 6 in the RX Delay Select (0x02AA) register. Note the value of the Maximum Delay over time is updated once per IMA frame, hence it an take up to one IMA frame for the value to be updated after it is reset. A value of 0xFE00 (negative 0) is read immediately after a reset command. The differential delays can be easily obtained by subtracting the delay values of the links.
3.3.13.6
Incrementing/Decrementing the Recombiner Delay
If a link to be added has a delay value which falls beyond the worst current delay value, then there are 2 options: either reject the link or re-adjust the pointers. To re-adjust the pointers, the number of cells to be added (delta) is specified and corresponds to the amount of extra delay to be added to the current recombination delay. The additional delay is first programmed in the Guardband/Delta Delay (0x0287-0x028E) registers and then a command to increase the delay is issued (using the Increment Delay Control (0x0281) and Decrement Delay Control (0x0282) registers). The ZL30226/7/8 device stops the recombiner process for the amount of time specified and then resumes the recombiner process. No cells are lost but there is an effect on the CDV. The increment process is completed when the control bit in the Increment Delay Control (0x0281) or Decrement Delay Control (0x0282) register is returned to a 0 value. If the link exhibiting the longest transmission delay is removed, the recombiner delay can be reduced accordingly. When such a correction occurs, the number of cells corresponding to the delay correction will be lost. To reduce the impact of this correction, its implementation can either be immediate or delayed. The Increment Delay Control (0x0281) and Decrement Delay Control (0x0282) registers are used for this purpose. The amount of delay to be removed (i.e., number of cells) in the recombiner process is controlled by the RX Guardband/Delta Delay (0x0287-0x028E) register. Alternatively, the links can all be placed in blocking mode for the transition period to avoid losing any cells. If a decrement delay command is issued which would result in a negative delay value on one or more links, the following action will take place: the read pointer is re-adjusted as required by the decrease delay command and since the delay is negative, the recombiner process is suspended until the delay on all the links at least reach a positive value of 4. Then, the recombiner process will resume.
3.3.14
RX IMA Group Start-Up
A quick initialization sequence for the RX IMA Group could be as follows (default values can be used for some registers). (Note: The startup procedure below is to indicate the most important steps. A more detailed and complete sequence can be found in the Zarlink IMA Core software).For ZL30226 only groups 0, 1, 2 and 3 are used. * * Configure the SRAM parameters using the SRAM Control (0x0299), RX External SRAM Control (0x0284) and Global Debug bit in the ICP Cell RAM DEBUG (0x0108) registers Configure the Cell delineation and IMA Frame State Machines parameters by writing to the Cell Delineation (0x00C9), Loss of Delineation (0x00C8) and IMA Frame Delineation (0x00CA) registers
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* * * * * Write to the RX Link Control (0x00C0-0x00C7) register to select the RX options
Data Sheet
Configure the RX serial port(s) by writing to the TDM RX Link Control (0x0700-0x070F) register Configure the RX IMA UTOPIA port by writing to the UTOPIA Output Group PHY Enable (0x0011) and UTOPIA Output Group Address (0x0008-0x000B) registers Validate the IMA parameter values received over the TDM links and configure the link in IMA mode using the RX Recombiner (0x0201-0x0208) and the RX Link Control (0x00C0 - 0x00C7) register When ready, start the recombiner process by writing to the RX Recombiner (0x0201-0x0208) register
3.3.15
Link Addition
The ZL30226/7/8 supports software controlled link addition to an existing RX link group. Such an addition can be used to increase available bandwidth. The added link receives Filler cells until the Far End (FE) TX side is active. During this time, the new link's delay is measured and compared with the current operating limits. The link is either rejected or accepted. The operational delay can be corrected if required as described in 3.3.13.6 Incrementing/Decrementing the Recombiner Delay. After synchronization is achieved, the added link can be included in the recombiner algorithm using bit 4 or 12 of the RX Recombiner (0x0201-0x0208) register. The link will be effectively included in the IMA Group when the corresponding bit in the Enable Recombiner Status (0x02AD) register is set. A link may also be added to an IMA Group when the first User cell is received. This is done by writing to the RX Recombiner Delay Control (0x0283) register.
3.3.16
Link Deletion
There are two reasons to deactivate a link: * * the bandwidth required decreases or an existing link becomes faulty.
Both link deactivation procedures specified in the IMA specification are supported under the control of software. The command to disable the recombination process for a link is issued by writing to bit 4 or 12 of the RX Recombiner (0x0201-0x0208) register. If the delay of the link to be removed is not the worst delay, then no pointer correction is required and the recombiner bit (i.e., bit 4 or 12 of RX Recombiner (0x0201-0x0208) register) for the removed link should be set to 0. If it is the worst case delay, then the pointer values could be corrected to reduce the amount of additional delay introduced by the recombiner. To do this, the pointers need to be changed (advanced). This results in reducing the number of cells (the amount of time) required for the recombiner process. To reduce the impact of this correction, its implementation can either be immediate or delayed. A command in the Increment Delay Control (0x0281) or Decrement Delay Control (0x0282) register is used for this purpose (refer to 3.3.13.6 Incrementing/Decrementing the Recombiner Delay, for more details).
3.3.17
Disabling an IMA Group
Before an IMA Group can be disabled, the software should ensure that no User cells are left in memory. As part of the higher level handshaking, the TX FE should have sent Filler cells for a while for the RX side to process all the User cells that could be in the external memory. The procedure to follow is to stop the recombination process and then wait for the enable process to be reported inactive (in the Enable Recombiner Status (0x02AD) register) before re-assigning the link to another IMA group or to TC Mode.
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3.4 The ATM Receive Path in TC mode
Data Sheet
Up to sixteen incoming serial (typically TDM) lines can be connected to the ZL30226/7/8 receiver and forwarded to the UTOPIA L2 interface served by an external ATM-Layer device. Figure 10 illustrates four of the sixteen possible UTOPIA ports that can be addressed through the UTOPIA Interface. The size of the RX UTOPIA FIFO is fixed at 4 cells. The Idle cells are automatically removed at the RX TDM block and all other valid received cells are transferred to the RX UTOPIA FIFO. The FIFO is cleared when the RX Utopia port associated with the FIFO is enabled.
RXCK DSTi RXCK DSTi RXCK DSTi RXCK DSTi S/P S/P S/P S/P Cell Delineation Idle Cell Removal
Cell Delineation
Idle Cell Removal UTOPIA Interface
Cell Delineation
Idle Cell Removal
Cell Delineation
Idle Cell Removal
System Clock
Figure 10 - Example of TC Mode Operation (Using Four of Sixteen Possible UTOPIA-Output Ports)
4.0
Description of the TDM Interface
The Transmit TDM blocks are independent of the Receive TDM blocks. The TX port of a framer can be connected to any of the ZL30226/7/8 TX UTOPIA Input ports and the RX port of a framer can be connected to any of the ZL30226/7/8 RX UTOPIA Output ports. The TDM interface provides a variety of modes to work with different x/DSL framers for various applications.There is one major mode: Non-framed mode which can be further divided into three minor modes.
4.1
Non-Framed Mode
ZL30226/7/8 support a non-framed mode where only a serial bit stream and clock are available for each link. Moreover, a wide range of data rate is supported by this mode, which makes it particularly useful in DSL applications where the line rate may vary. Mapping registers must all be set to 0xFFFF in Non-framed mode. Serial clock rate and data rate must be the same. Moreover, bit mode cell delineation (bit 10 in TDM RX Link Control registers) must be selected, and register 0x0741 must be written by 0x36. Three minor modes are available in Non-framed mode, resulting to different data rate and link number.
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4.1.1 Non-Framed Mode - 2.5 Mbps
Data Sheet
In Non-framed mode, all links are able to run from 0 up to 2.5 Mb/s. On the transmit side, if the TXCK is programmed as input. The transmitter will be "free running" and will output serial data continuously. This mode is selected in TDM TX Link Control (0x0600-0x060F) and TDM RX Link Control (0x0700-0x070F) by the following settings. Data rate (bits 6:5) = 01 Multiplex mode (bits 4:3) = 00 Cell delineation mode (bit 10 of TDM RX Link Control only) = 1
4.1.2
Non-Framed Mode - 5.0 Mbps
If a serial link of more than 2.5 Mbps but less than 5.0 Mbps data rate is required, this mode can be applied. For every two links in a pair, one is disabled and the other is able to run from 0 up to 5.0 Mb/s. The links that are paired are pre-determined: link 0 with link 1, link 2 with link 3 and so on. The link that will remain enabled in each pair is also pre-determined. They are link 0, 2, 4, 6, 8, 10, 12 and 14. For the pair of link 0 and link 1, the pins associated with link 1 cannot be used and are tri-stated. On the transmit side of link 0, if the TXCK is programmed as an input, the transmitter will be "free running" and will output serial data continuously. The same logic applies to the other pairs. For any disabled link, its associated registers are all disabled, except for mapping registers that must be set to all ones. No other configuration is necessary for disabled links. When the link is part of an IMA group, then both links that are paired have to be assigned to the same IMA group number. This is done by writing to the RX Recombiner Register (0x0201-0x0208). This mode is selected in TDM TX Link Control (0x0600-0x060F) and TDM RX Link Control (0x0700-0x070F) by writing the following settings into those enabled links only. Data rate (bits 6:5) = 10 Multiplex mode (bits 4:3) = 00 Cell delineation mode (bit 10 of TDM RX Link Control only) = 1
4.1.3
Non-Framed Mode - 10.0 Mbps
If a serial link of more than 5 Mbps but less than 10.0 Mbps data rate is required, this mode can be applied. For every four links in a group, three are disabled and the other is able to run from 0 up to 10.0 Mbps. The four links that can be grouped are pre-determined: link 0, 1, 2, 3 are one group; link 4, 5, 6, 7 are one group and so on. The link that will remain enabled in each group is also pre-determined. They are link 0, 4, 8 and 12. For the group of link 0, 1, 2 and 3, the pins associated with link 1, 2 and 3 cannot be used and are tri-stated. On the transmit side of link 0, if the TXCK is programmed as an input, the transmitter will be "free running" and will output serial data continuously. The same logic applies to the other groups. For any disabled link, its associated registers are all disabled, except for mapping registers that must be set to all one. No other configuration is necessary for disabled links. When the link is part of an IMA group, then the four links that are grouped have to be assigned to the same IMA group number. This is done by writing to the RX Recombiner Register (0x0201-0x0208).
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ZL30226/7/8
Data Sheet
This mode is selected in TDM TX Link Control (0x0600-0x060F) and TDM RX Link Control (0x0700-0x070F) by writing the following settings into those enabled links only. Data rate (bits 6:5) = 11 Multiplex mode (bits 4:3) = 00 Cell delineation mode (bit 10 of TDM RX Link Control only) = 1
4.2
Clock format
The TXCK signal can be programmed to be either output or input. In the generic modes, the clock polarity can be selected to have a rising or falling edge at the bit boundary.
4.3
TDM Loopback Mode
Two loopback modes are provided where the TDM RX inputs are internally routed back to the TDM TX outputs (remote loopback) with the RX block fully operational, and where the TDM TX outputs are routed back to the TDM RX inputs for test purposes (metallic loopback). The TX and RX links have to be programmed in the same mode for the loopback to operate properly. Bit 8 of the TDM TX Link Control Register (0x0600-0x060F) controls the remote loopback and bit 8 of the TDM RX Link Control (0x0700-0x070F) register controls the metallic loopback. To use remote loopback, TXCK must be configured as output sourcing from the RXCK of the same port. The loopback is on a per link basis with the limitation that physical links are paired: i.e. TX link 0 is connected to RX link 0 and so on. Besides TDM loopacks, there is also a UTOPIA loopback described in the section 5.7.
4.4
.Serial to Parallel (S/P) and Parallel to Serial (P/S) Converters
Each serial TDM link has assigned S/P and P/S units. The P/S unit takes a byte from the cell RAM and converts it to a serial bit stream. The S/P unit takes a byte from the DSTi input and converts it to parallel format for use by the Cell Delineation block. P/S and S/P units can be set-up differently on a per port and per direction basis (i.e. the transmit and receive function of the same port can use different configurations). The following features are supported: * * * enabling/disabling the P/S and S/P units (if they are disabled the associated outputs are Tri-stated) independently programming the polarity of RXCK and TXCK signals (Generic TDM mode only) generating/accepting TXCLK signals to support most xDSL framers (depending on the programmed mode)
When the TXCK signals are outputs, the source for the TXCLK is software selectable from any of the RXCK inputs or any of the four external REFCKs.
4.5
Clocking Options
TXCK can be either input or output signal. When TXCK are inputs, they are generated by external circuitry. When TXCK are outputs, TXCK source is software selectable and can be any of the RXCK signals or four external REFCK inputs (see Figure 11). The RXCK pins are always defined as inputs and the proper signal must be provided to each input.
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Data Sheet
Cell Delineation
S/P
DSTi RXCK
TX Cell FIFO
P/S
DSTo
RXCK 0-15 REFCK 0-3
TXCK
RXCK 0-15
PLLREF0 PLLREF1
Figure 11 - TXCK Output Pin Source Options
4.5.1
Primary and Secondary Reference Signals
Two output pins are provided to simplify the external circuitry required when using an external PLL. These two pins, PLLREF0 and PLLREF1, re-route any of the RXCK signals and drive the primary and secondary reference signals of a PLL under software control. Refer to Section 8, Application Notes, for examples.
4.5.2
Verification of Clock Activity
The ZL30226/7/8 implements circuitry to determine whether or not a selected clock signal is active. This feature is used to ensure a clock is operational before using it as a source for one or more transmit links. A read of the TXCK Status (0x0630), RXCK Status (0x0631) or REFCK Status (0x0632) register indicates clock activity if a bit is '1'. A value of '0' for these bits means that no transition was observed on this clock. This circuitry does not measure the frequency of a clock signal, it only detects activity on the TXCK, RXCK and REFCK signals.
4.5.3
Clock Selection
The clock selection circuitry selects the desired clock signal and ensures a smooth, glitch free, transition between the current clock source and the new clock source. Clock source activity can be verified using the TXCK Status (0x0630), RXCK Status (0x0631) or REFCK Status (0x0632) registers.
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5.0 UTOPIA Interface Operation
Data Sheet
The ZL30226/7/8 supports the UTOPIA L1 and L2 Mode, 8 or 16-bit wide bus, with odd/even parity, for cell level handshake only. In 8-bit UTOPIA mode maximum supported clock is up to 52 MHz and in 16-bit mode it is 33 MHz. Each port can be assigned an address ranging from 0 to 30. The address value of 31 is reserved and should not be used. The TX and RX paths of each IMA Group and each link in TC has its own PHY address. These PHY addresses are defined in the UTOPIA Input Link Address (0x0040-0x0047) registers, UTOPIA Input Group Address (0x0048-0x004B) registers, UTOPIA Output Link Address (0x000-0x0007) registers, and the UTOPIA Output Group Address (0x0008-0x000B) registers. The UTOPIA Input LINK PHY Enable (0x0050) and the UTOPIA Output Link PHY Enable (0x0010) registers are used to enable the PHY Address of the links in TC mode. The UTOPIA Input Group PHY Enable (0x0051) register and the UTOPIA Output Group PHY Enable (0x0011) registers are used to enable the PHY Address of the IMA Groups. The ZL30226/7/8 UTOPIA port uses handshaking signals to process data streams. The start of a cell (SOC) is marked by the UTOPIA SOC sync signal. This signal is active during the transfer of the first byte/first word of a cell. The 52 bytes/26 words that follow the arrival of the first byte/first word of a cell are interpreted as belonging to the same cell and are stored accordingly. The Cell Available status line (Clav) is used to communicate to the ATM controller whether the ZL30226/7/8 has space for a cell in the PHY address that was polled in the previous cycle. Whenever there is space for a cell in the TX direction or a cell ready in the RX direction, the TXClav and/or RXClav signal will be driven High. If there is no space in Tx direction and/or no cell is ready in Rx direction, the TxClav and/or RxCLav will be kept low.When the address does not correspond to any enabled PHY address inside the ZL30226/7/8, the TXClav and RXClav signal are set to High impedance mode. The use of an external pull-down may be required for the proper operation of the Utopia bus in MPHY mode. Note that the transmit or receive Utopia clock frequencies do not have to be synchronized with the system clock by their frequencies cannot exceed the system clock frequency. Important Note: The ZL30226/7/8 doesn't support the back-to-back mode on Rx side(ATM output port). Depending on which ATM controller the ZL30226/7/8 interfaces to, there might be interoperability issues that affect the receive side communication. For details, please refer to Technical Note ZLAN-88: UTOPIA Interface between MT90224/3/2 and Specific ATM Controllers. This application note is covering the ZL30226/7/8 as well.
5.1
ATM Input Port
The UTOPIA interface input clock TxClk is independent of the system clock. The UTOPIA TxClk can be up to 52 MHz for 8-bit mode and up to 33 MHz for 16-bit mode. The incoming cell is stored directly in the internal TX Cell RAM where the TX UTOPIA FIFOs are implemented. The UTOPIA transmit clock (TxClk) is checked against the system clock. If the incoming byte clock frequency is lower than 1/128 of the system clock, bit 2 of the General Status (0x040E) register will be set. This bit is cleared by overwriting it with 0. This aids in debugging as the presence of a UTOPIA clock is required not only for data transfer but also for proper operation of the UTOPIA registers. The total space for the UTOPIA input cells for all IMA Groups and links in TC mode is 118. These 118 cells are shared between 24 TX UTOPIA FIFOs and 16 TX Link FIFOs. The size (length) of each TX UTOPIA FIFO is defined by writing to the TX IMA Group FIFO Length Definition (0x0093 - 0x0096) registers. The maximum value is 6 and the minimum value is 0 (in the case the PHY port is not to be used). The size of the TX Link FIFO is defined on a per group using the TX IMA Control (0x0321-0x0324) registers.
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Data Sheet
The device will not accept a cell from the UTOPIA Interface if the internal Cell Ram is full. Status bit 0 in the General Status (0x040E) register is set to 1 to indicate the 'no free cell in TX Cell RAM' condition. The status bit can be cleared by overwriting it with 0. Note that the internal FIFO level on the TX direction is updated after the complete cell is received. If the corresponding Utopia port address is poled, that the Cell Available Status signal could reflect space available whereas the FIFO should be reported full. If a cell transfer is initiated under these conditions, the cells will be accepted and the next time the Utopia port is polled, the Cell Available Status signal will report the correct state of the FIFOs. The UTOPIA Input block has the option to verify the HEC of the cell coming from the ATM layer. Four different options are available and are selected by bits 1 and 0 of the UTOPIA Input Control (0x0052) register. * The '00' option is used to always accept a cell from the ATM layer. The HEC is verified and if wrong, the UTOPIA Input counter associated with the UTOPIA port for cells with bad HEC is incremented. The ZL30226/7/8 will re-generate a valid HEC based on the content of the 4-byte header that was received. The '01' option is used to verify the HEC of an incoming cell. If the HEC value is wrong and if it can be corrected (1 bit error), then the cell is corrected and accepted as a good cell. The bad HEC counter is not incremented if the HEC is corrected. The bad HEC counter is incremented if the HEC value cannot be corrected. In this mode, the cell is always accepted. The ZL30226/7/8 will re-generate a valid HEC based on the content of the 4-byte header that was received. The '10' option is used to verify the HEC on the incoming cell and discard the cell if the HEC value is wrong. The bad HEC counter is incremented if a cell is discarded. The '11' option is similar to mode '01' except that if the HEC value cannot be corrected, then the cell is discarded. If the HEC value is corrected, the bad HEC counter is not incremented.
*
* *
5.2
ATM Output Port
The ZL30226/7/8 supports a 53 byte/27 word cell stream via the ATM output port. Cells received at the ATM output port are stored in the RX UTOPIA FIFO before being processed by the UTOPIA Interface. The output of the UTOPIA Interface can be stopped by the ATM Layer device by de-asserting the RxENB* signal. The start of a cell is marked with the SOC signal, which is active during the transmission of the first byte/first word of a cell. The following 52 bytes/26 words are belonging to the same cell. The RX byte clock (RxClk) can be up to 52 MHz and is checked against the system clock. If the incoming byte clock frequency is lower than 1/128 of the system clock, bit 3 of the General Status (0x040E) register will be set. This bit is cleared by overwriting it with 0. This aids in debugging as the presence of a UTOPIA clock is required not only for data transfer but also for proper operation of the UTOPIA registers. Overflow conditions in the RX UTOPIA FIFO associated with any of the 24 PHY RX Addresses cause a status bit to be set in either the IRQ Link TC Overflow Status (0x0410-0x041F) or IRQ IMA Overflow Status Registers (0x0420-0x0427) register. These status bits are cleared by overwriting them with 0. Additionally, for each status bit there is an Interrupt Enable bit in the associated IRQ Link TC Overflow Enable (0x0434) or RX UTOPIA IMA Group FIFO Overflow IRQ Enable (0x040C) register. When enabled, the status bit is reported in an Interrupt register. See section 6.2 Interrupt Block for more details. The size of the RX UTOPIA FIFO is fixed at four cells for the TC PHY Addresses and four cells for the IMA Group PHY Addresses. Note that in the receive direction, the parity bit that is generated is not valid if the receive Utopia clock is faster than 50 MHz.
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5.3 UTOPIA Operation With a Single PHY
Data Sheet
A single ATM layer device with a UTOPIA L2 MPHY port can be connected to the ATM input port of one ZL30226/7/8. Another ATM-Layer device using the UTOPIA L2 MPHY input interface is used to receive ATM cells from the ZL30226/7/8. The address pins should be set to the value programmed by the management interface.
5.4
UTOPIA Operation with Multiple PHY
When more than one ZL30226/7/8 is connected to a single ATM Layer device the single TxClav and RxClav scheme is used. Direct Status Indication and Multiplexed Status Polling schemes are not supported. The necessary polling is performed by the ATM-Layer device. The UTOPIA Interface transmit and receive addresses, provided by the ATM-Layer device, are used to de-multiplex the ATM-cell stream to as many as eight ZL30226/7/8s (as limited by the UTOPIA L2 specification's maximum of eight device loads and 31 addresses). The maximum total available bandwidth for the serial lines served by each ZL30226/7/8 device is 40 Mbits/s (totalling 5 MBytes/s per ZL30226/7/8 device).
5.5
UTOPIA Operation in TC Mode
In TC Mode, each Utopia port inside an ZL30226/7/8 corresponds to a physical serial TDM (xDSL) line. Up to sixteen PHY ports can be supported by one ZL30228. Up to eight ZL30226/7/8s can be connected to a UTOPIA bus. The ports in the same device represent only one electrical load on the UTOPIA bus.The ZL30226/7/8 supports the up to 31 PHY addresses as per UTOPIA specification. Please also refer to Technical Note ZLAN-88: UTOPIA Interface between MT90224/3/2 and Specific ATM Controllers, as there might be some limitations on maximum number of output PHY addresses supported depending on the type of ATM controller that is interfaced with ZL30226/7/8. The MPHY address at the input port of ZL30226/7/8 (TxAddr[4:0]) is used to store the cell in one specific TX UTOPIA FIFO. The MPHY address at the output port (RxAddr[4:0]) is used to retrieve the cells from the proper RX UTOPIA FIFO.
5.6
UTOPIA Operation in IMA Mode
In IMA mode, many ZL30226/7/8s, with up to eight UTOPIA ports each (one port per IMA Group), can be served by an external UTOPIA L2 ATM-Layer device provided the UTOPIA limitation of 31 ports in total is observed. This provides up to 31 different logical IMA-channels. Note that port 31 (1F in hexadecimal format) is reserved. Please also refer to Technical Note ZLAN-88: UTOPIA Interface between MT90224/3/2 and Specific ATM Controllers, as there might be some limitations on maximum number of output PHY addresses supported depending on the type of ATM controller that is interfaced with ZL30226/7/8.
5.7
UTOPIA Loopback
With UTOPIA loopback enabled, the Tx UTOPIA port will accept cells and loop these back to the Rx UTOPIA
interface. The Rx UTOPIA interface will then output these cells.The UTOPIA loopback is enabled by setting the bit 9 in UTOPIA Input Control Register (0x0052). With UTOPIA loopback, only one PHY address can be tested at a time.
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5.8 Examples of UTOPIA Operation Modes
Data Sheet
Figure 12 shows the connection of one ATM Device to one ZL30228.
ATM Layer
TxClk TxEnb* TxAddr TxClav TxData TxSOC ATM Rxclk RxEnb* RxAddr RxClav RxData RxSOC
Physical Layer
Framer ZL30228 . . . . . Framer
Figure 12 - ATM Interface to ZL30228 Figure 13 shows the connection of one ATM Device with more than one ZL30228.
ATM Layer
Txclk TxEnb* TxAddr TxClav TxData TxSOC ATM Rxclk RxEnb* RxAddr RxClav RxData RxSOC Txclk TxEnb* TxAddr TxClav TxData TxSOC
Physical Layer
Framer ZL30228
. . Framer
Framer ZL30228 . .
Rxclk RxEnb* RxAddr RxClav RxData RxSOC
Framer
Figure 13 - ATM Interface to Multiple ZL30228s
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Data Sheet
3 UTOPIA Ports (3 Links in TC Mode) (TC) ATM Layer Device
1 UTOPIA Port (IMA Group #1) 1 UTOPIA Port (IMA Group #2)
(8 links) 16 (5 links)
Framer
Figure 14 - ATM Mixed-Mode Interface to One ZL30228 Figure 14 illustrates the implementation of a mixed mode using only 1 ZL30228. Links that are not used for IMA Groups are available in TC mode. Unused links are programmed to set their outputs to high impedance mode.
6.0
6.1
Support Blocks
Counter Block
The ZL30226/7/8 includes 224 24-bit counters to provide statistical information on the device's operation. All the counters are cleared by a hardware reset. A maskable interrupt can be generated when the counter overflows. Counters can also be latched to capture the state of all registers at once. A predetermined value can also be loaded into a counter. This feature can be used to generate an interrupt after a specified number of cells is processed. Counter values are incremented by 1 for every event occurrence and, when the count reaches all 1's, will overflow (to all 0's).
6.1.1
UTOPIA Input I/F counters
There are four counters associated with the each of the 24 UTOPIA Inputs (from ATM layer to the ZL30226/7/8) for a total of 96 counters. These counters record the following information: * * * * the total number of cells or the total number of user cells received at the UTOPIA Input I/F the total number of Idle Cells received at the UTOPIA Input I/F, removed or not the total number of Unassigned Cells received at the UTOPIA Input I/F, removed or not the number of cells having a single or multiple bit error in the HEC, removed or not but not including the cells where the HEC is corrected
6.1.2
Transmit TDM I/F Counters
There are four counters associated with the each of the sixteen transmit TDM links for a total of 64 Transmit counters. These counters record the following information: * * * * the the the the total total total total number number number number of of of of cells sent through the TDM link Idle/Filler cells or the total number of user cells sent through the TDM link Stuff cells sent through the TDM link ICP cells sent through the TDM link
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6.1.3 Receive TDM I/F Counters
Data Sheet
There are four counters associated with each of the sixteen receive TDM links for a total of 64 receive counters. These counters record the following information and are active as soon as the RX TDM port is enabled: * * * * the total number of cells received through the TDM link or total number of Stuff events received on the link the total number of Idle/Filler cells received through the TDM link, with good or bad HEC or the total number of user cells the total number of ICP Cells with violation received through the TDM link the total number of cells with wrong HEC, discarded or not, received through the TDM link but not including the cells where the HEC is corrected
Note that the number of Stuff cells is included in the total number of User cells.
6.1.4
Access to the Counters
Accessing (READ) counters is a three step operation. First, the desired counter must be selected by writing to the Select Counter Register (0x0432). Second, the READ command ('0x00x101') is written to the Counter Transfer Command (0x040F) register. This command causes the current three byte count value to be copied from the specified counter to the two 16 bit-wide Counter Upper Byte (0x0430) and Counter Bytes 2 and 1 Register (0x0431) registers (note that this value is unchanged until another counter read command is issued). And third, the Counter Upper Byte (0x0430) and Counter Bytes 2 and 1 Register (0x0431) registers are read to obtain the three byte count value of the selected counter. Pre-loading (WRITE) a counter is also a three step function. First, the three byte pre-load value is written to the two 16 bit-wide Counter Upper Byte (0x0430) and Counter Bytes 2 and 1 Register (0x0431) registers. Second, the identification of the counter to be pre-loaded is written to the Select Counter Register (0x0432). And third, the WRITE command ('0x00x001') is written to the Counter Transfer Command (0x040F) register. The IRQ enable bit of a counter is set, or reset, by selecting the counter and writing to the appropriate bit of the Counter Transfer Command (0x040F) register. The value '0x001010' enables the counter IRQ and 'xxx00010' disables (masks) it.
6.1.5
Latching counter mode
An additional mode of operation is available in the counter block where the values of all the counters are transferred, all at the same time, to a series of internal registers. The transfer can be initiated automatically based on an input signal or following a transfer command under software control. The transfer mode can be disabled to utilize the counters in the same method as in the MT90220/221. When the source for the latch command is from the dedicated input pin, the user has the option to use directly this signal as a latch command or to divide the incoming signal by 8000 before generating the latch command (for example, using a 8 kHz F0 frame pulse signal to create 1 second intervals). Bits in the Counter Transfer Command (0x040F) register are defined to support these new features. The counters are 24 bits wide when operated without the latching option and are 16-bits wide when the latching feature is enabled. After each latch signal, the counters are reset to 0 in order to report the number of events between two latch commands. Before the latching mode is enabled, the counters may be loaded (or reset), but the software should not write to the counters after the latching mode is enabled.
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Data Sheet
Note: The content of the counter for all cells in the Utopia Transmit block for the IMA Group 7 is not reset by the latch command when the counters are operating in latch mode. The counter will contain a cumulative count of the ATM cells that were received on the corresponding Utopia port address. This counter is defined by the value 0x0177 in the Select Counter Register (0x0432).
Link 15 Link 14 Link 13 ....... Link 3 Link 2 Link 1 Link 0 1 UTOPIA RX FIFO Overflow 4 UTOPIA Counters 4 TX Counters 4 RX Counters S T A T U S
16 x IRQ Link Registers
1 x IRQ Master Registers
Link 15 S T A T U S E N A B L E
TC Link Overflow Status LCD LIF LODS IV New RX ICP Overflow in ICP pre-proc READY BIT/ICP CELL TIME *
IMA GRP CNTRS * End of LCD End of LIF End of LODS 11
0 S T A T U S
E N A B L E
IRQ PIN
Link 0
Note *: These 2 IRQ signals are only present in IRQ Link Status register (0x0435) for Link 0.
UTOPIA IMA Group Counters Frame Pulse Transfer Done 7S T 0A 7T U 0S E N A B L E E N A B L E S T A T U S S T A T U S 1 UTOPIA RX FIFO Overflow 4 UTOPIA Counters
7
TX ICP Cell
Handler Register
0 IMA Group IMA OVERFLOW OVERFLOW 1 set of registers 8 registers
Figure 15 - IRQ Register Hierarchy
6.2
Interrupt Block
The ZL30226/7/8 can generate interrupts from many sources. All interrupt sources can be enabled or disabled. Write action is required to clear the source of interrupt. Interrupts are grouped on a per link basis, with six sub-categories for each link and two special types for the IMA Group configuration. These special interrupts are only present in the Link 0 IRQ Status register. Refer to Figure 15 for a representation of the interrupt register hierarchy.
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6.2.1 IRQ Master Status and IRQ Master Enable Registers
Data Sheet
There is a IRQ Master Status (0x0455) register that reports interrupts generated by any event on any of the links. Each bit of this register corresponds to a link. A '1' in a bit position indicates that the associated link is reporting an interrupt condition. For each bit in the IRQ Master Status (0x0455) register, there is a corresponding bit in the IRQ Master Enable (0x0433) register. When any IRQ source is active and the corresponding Enable bit is '1', then the IRQ pin will go LOW (active). The IRQ Master Status (0x0455) register always reports the current state of the source(s) of interrupt. It does not latch the interrupt request(s); it only reports that one or more bit(s) in one or more IRQ Link Status register(s) is (are) set. The bits that are read as active ('1' value) are cleared when the source of the interrupt is cleared or when the corresponding bit(s) in the IRQ Link Enable (0x0445-0x0454) register(s) is (are) set to 0. Writing to or reading from the IRQ Master Status (0x0455) register has no effect on the level of the interrupt pin.
6.2.2
IRQ Link Status and IRQ Link Enable Registers
There are sixteen IRQ Link Status (0x0435-0x0444) and sixteen IRQ Link Enable (0x0445-0x0454) registers; one of each per link. The following six types of interrupts are reported (in the six least significant bits of the IRQ Link Status registers) for each link: * * * * * * * * * Bit 11 latched: reports the end of an LODS (Link is Out of Delay Synchronization) condition on a RX TDM link. Bit 10 latched: reports the end of an LIF (Loss of IMA Frame) condition on a RX TDM link Bit 9 latched: reports the end of an LCD (Loss of Cell Delineation) condition on a RX TDM link Bit 6 latched: reports an overflow in the ICP pre-processing RAM Bit 5 latched: reports that an ICP Cell with changes was received on a RX TDM link Bit 4 latched: reports an IV (ICP Cell violation) condition on a RX TDM link Bit 3 latched: reports an LODS (Link is Out of Delay Synchronization) condition on a RX TDM link Bit 2 latched: reports an LIF (Loss of IMA Frame) condition on a RX TDM link Bit 1 latched: reports an LCD (Loss of Cell Delineation) condition on a RX TDM link
Bit 0 (LSB) is a status bit. It reports an interrupt for an overflow condition in one or more of the 24 counters associated with the link. It is also used to report an overflow condition in the UTOPIA RX FIFO associated with a TDM link in TC mode. If enabled, a counter generates an interrupt request when it overflows (i.e., starts over from 0 after reaching the maximum counter value). See 6.1 Counter Block paragraph for more details on the operation of the counters. These 13 sources of overflow can be identified through the IRQ Link FIFO Overflow and IRQ UTOPIA FIFO Overflow status registers. Reading the IRQ Link Status (0x0435-0x0444) register does not clear the source of interrupt. The bit 0 status is reset by any one of the following procedures: * * * disabling (masking) the IRQ for this specific counter clearing the overflow status bit in the IRQ Link TC Overflow Status (0x0410-0x041F) registers disabling the interrupt in the IRQ Link TC Overflow Enable (0x0434) or in the corresponding Link (in TC mode) Counter registers
Bits 1 to 6 and 9 to 11 of the IRQ Link Status (0x0435-0x0444) registers are latches that report the source of an interrupt. Writing a '0' these bits will reset the status bit (will reset the latch). Writing '0' to bit 0 has no effect on the status bit.
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Data Sheet
Writing a '1' has no effect on the bits 0 to 6 and 9 to 11 of the IRQ Link Status (0x0435-0x0444) register. Each one of these 10 interrupt sources can be enabled by writing a '1' in the IRQ Link Enable (0x0445-0x0454) registers to the bit corresponding to the interrupt source. In some situations, an interrupt source can be masked as part of an interrupt service routine. This makes it possible to detect further interrupts of higher priority. For example, if an interrupt for a counter is received, the source of the interrupt can be masked by writing 0 to the corresponding bit and then starting a separate process outside of the Interrupt Service Routine. The independent process would read, reload and re-enable the counter to produce another interrupt service request, if necessary. At the end of this process, the enable bit in the IRQ Link Enable (0x0445-0x0454) register would be set to '1' to detect any future interrupt requests.
6.2.2.1
Bit 8 and 7 of IRQ Link 0 Status and IRQ Link 0 Enable Registers
Bits 8 and 7 of the IRQ Link 0 Status (0x0435) register have a special operation. Bit 8 reports an overflow condition in any of the counters or UTOPIA RX FIFOs associated with one of the eight IMA Groups. Refer to IRQ IMA Group Overflow Status (0x0457) and IRQ IMA Group Overflow Enable (0x040B) registers for more details. Bit 8 is a status bit and is cleared by disabling the IRQ for this specific counter or disabling (masking) the FIFO overflow condition by writing to the RX UTOPIA IMA Group FIFO Overflow IRQ Enable (0x040C) register. Bit 7 is used to report the following two event types: * * the ICP cell internal transfer is complete (reported by any IMA Group TX ICP Cell Ready bit) the end of an IMA frame on the reference link of an IMA Group
The second type of event assists in implementing the software counter required to verify that Group Status and Control field information is sent for at least 2 consecutive IMA frames. The sixteen interrupt sources are enabled independently by writing to the TX ICP Cell Interrupt Enable (0x0088) register and the TX IMA Frame Interrupt Enable (0x0089) register. Note that both interrupts from the IMA Frame and the ICP Cell internal transfer have to be enabled for an interrupt to be generated. There is also an associated Control/Status register (TX ICP Cell Handler (0x0086) register) that reports the interrupt source and the state of the transfer of an ICP Cell or the occurrence of the end of an IMA frame. The Frame status bits are cleared by writing 0 to the bit. The Ready bit is set to 1 when the transfer is complete. Bit 6 is a latched bit in the IRQ Link 0 Status (0x0435) register and is cleared by overwriting it with 0. Each of these two interrupt sources can be masked by writing a '1' to the bit corresponding to the interrupt source in the IRQ Link 0 Enable (0x0445) register.
6.2.3
IRQ Link TC Overflow Status Registers
The IRQ Link TC Overflow Status Registers (0x0410 - 0x041F) report the overflow condition from any of the counters associated with the TX TDM link, the RX TDM link or the TX UTOPIA I/F. They also report the overflow condition from the level of the UTOPIA RX FIFO when the link is used in TC mode. The 13 interrupt sources are organized as follows: * * * * 1 bit (12) for the RX UTOPIA FIFO for TC mode overflow 4 bits (11:8) for the UTOPIA Input Counters 4 bits (7:4) for the TX TDM Link Counters 4 bits (3:0) for the RX TDM Link counters
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6.2.4 IRQ IMA Group Overflow Status and Enable Registers
Data Sheet
The sources of IMA Group overflow conditions are organized in two levels of registers: * * eight low level, 5-bit registers (one register per IMA Group) one intermediate 4-bit register that is used to report the overflow conditions for each IMA Group to minimize the number of accesses when identifying the source of an overflow condition
The IRQ IMA Group Overflow Status (0x0457) register indicates which one of the eight IMA Groups is reporting an overflow condition. When enabled, the bits in this status register reflect any overflow condition reported by the IRQ IMA Overflow Status (0x0420-0x0427) registers. The IRQ IMA Group Overflow Enable (0x040B) register is used to enable any overflow conditions for a specific IMA Group. Each of the four bits correspond to one of the eight IMA Groups. A value of '1' enables the report of the overflow condition to the upper IRQ levels.
6.2.5
IRQ IMA Overflow Status and RX UTOPIA IMA Group FIFO Overflow Enable Registers
There are five possible sources of overflow conditions that can be reported for each IMA Group. The IRQ IMA Overflow Status (0x0420-0x0427) register captures (latches) the overflow condition from any of the four counters associated with the UTOPIA TX I/F when the TDM link is used in IMA mode. It also latches when an overflow condition occurs in the RX UTOPIA FIFO associated to a TDM link when in IMA mode. The status bit is cleared by overwriting it with a 0. Reading the registers or writing a '1' to these registers will not change the content of the registers. A counter generates an interrupt request, if not masked, when the counter overflows (i.e. starts over from 0 after reaching the maximum counter value - refer to paragraph 6.1 for more details on the operation of the counters). An interrupt request can also be generated, if not masked, when an overflow condition is detected in the UTOPIA RX FIFO associated with an IMA Group. There is one enable register used to enable the generation of an interrupt by the overflow condition of the RX UTOPIA FIFO associated with an IMA Group. This is the RX UTOPIA IMA Group FIFO Overflow IRQ Enable (0x040C) register.
6.3 6.3.1
Microprocessor Interface Block Access to the Various Registers
Since the ZL30226/7/8 and microprocessor operate from two different clock sources, access to a ZL30226/7/8 register is asynchronous. Data is synchronized between the ZL30226/7/8 and the microprocessor using either direct or indirect (synchronized) methods of access. The direct method is used during a read access whenever data does not change or data changes do not represent any problem. There is no register that clears status bits upon a read access. A write action is always required to clear a status bit. The indirect method is identified with 'S' (indirect and need to synchronize with a ready bit) whereas the direct access is identified with a 'D' in the register tables.
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Zarlink Semiconductor Inc.
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6.3.2 Direct Access
Data Sheet
Direct access registers can be written or read directly by the microprocessor, without having to use other registers. Upon a write access to the ZL30226/7/8 internal registers, the data is stored in an internal latch and transferred to the destination register within 2.5 system clock cycles (50 nsec at 50 MHz). No specific action is required if the microprocessor provides at least 50 nsec (with Chip Select signal inactive) between 2 consecutive write accesses or between a write and a read back of the same register. If the microprocessor is faster, then consecutive accesses must be inhibited or wait state(s) introduced (this option is available on most MCUs).
6.3.3
Indirect Access
Indirect access registers cannot be accessed directly by the microprocessor. The value is transferred back and forth using registers which hold a copy of the information (data) and internal address of the register. This is required to stabilize the read value. Consider for example the transfer of a TX ICP cell that requires almost 200 system clock cycles. A dedicated ready bit which can optionally generate an interrupt is implemented for this type of transfer. Accessing any of the 24-bit counters provides another example. A ready bit is implemented in the Counter Transfer Command register when the transfer is completed. When accessing indirect registers specified by the RX Delay Select (0x02AA) or RX Delay Link Number (0x0286) registers, the value in the indirect registers can be read when the write to the selection register is effectively done (i.e., 2.5 system clock cycles after the write cycle is completed). There is no additional delay required.
6.3.4
Clearing of Status Bits
The status bits will remain set until cleared by a specific write action from the microprocessor. Status bits are cleared by overwriting a zero to the corresponding position in the source register. Each input status register has a related interrupt enable register. When enabled, setting a bit in the interrupt enable register causes an interrupt to occur in the corresponding status register bit.
6.3.4.1
Toggle Bit
Some registers include a toggle bit. Toggle bits are used to indicate a write action to any internal register has taken place. Typically, this bit is toggled 2.5 system clock cycles after performing the write action. To use the toggle bit, its state (either 0 or 1) must be read (polled) and its state is changed (toggled) when a write command is completed. This bit is particularly useful when the processor clock is much faster than the ZL30226/7/8 system clock.
6.4
Cell Preprocessor Block
The ICP Cell is used in the IMA protocol to exchange information to maintain proper operation between the Far End and the Near End of the IMA group. One byte, the SCI byte, is used to indicate when there is new information to be processed in the incoming ICP cell and it is monitored by the IMA software to determine when to process an incoming ICP cell. In the normal mode of operation, the SCCI byte is monitored and an interrupt is generated whenever the value of the byte had changed. The software has to read most of the bytes of the new ICP cell to determine which bytes had changed and take appropriate action. To simplify the monitoring process of the ICP cell, the ZL30226/7/8 includes an option to compare, on a per byte by byte basis, the most recent incoming cell placed in the RX ICP Cell buffer with the previous cell written in the same buffer. The cells that are placed in the RX cell buffer are selected based on the criteria specified in the RX Cell Type RAM (0x0100-0x0101) registers. Another option can be selected where bytes 8, 52 and 53 are not compared and are not reported. Byte 8 contains the IMA Frame Sequence number. It is used for the IMA Frame State Machine and is not used by the Link or Group State Machines. Bytes 52 and 53 contain the CRC-10 and are not required by the user. The RX Cell Processor can be enabled on a per link basis.
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Zarlink Semiconductor Inc.
ZL30226/7/8
Data Sheet
When the new byte is different, a copy of the new byte along with the byte number is put into a dedicated preprocessor FIFO, accessible via the Processed RX Cell Link FIFO (0x0140 - 0x014F) registers. There is one preprocessor FIFO (circular buffer) of 64 entries per RX Link. Each FIFO entry is 16-bits wide and the ZL30226/7/8 increments automatically the internal pointer to point to the next entry for the next read access. The Least Significant Byte (bits 7 to 0) contains the newly received byte that was found to be different. Bits 13 to 8 contain the byte position in the ATM Cell. The numbering scheme goes from byte #1 to byte #53. The bit 14 is used as a flag to indicate the last byte that was found to be different in the newly received ATM cell that was put in the RX Cell buffer. Bit 15 is used to indicate if there are more bytes in the FIFO. A value of "0" indicates the last valid byte (the FIFO is empty) and a value of "1" indicates that there are more bytes to be read. See below for a representation of a word read from the FIFO.
15 14 13 12 11 10 9 8
76543210
Byte content from the latest RX Cell Position in Cell for the byte found to be different (number range between 1 and 51) When set, indicates the last byte reported for the current processed cell. When clear (0), indicates that the FIFO associated with this link is empty (no more bytes to be read) Processed RX Cell FIFO Word Format
Figure 16 - Processed RX Cell FIFO Word Format When the pre-processing option is enabled, (using the RX Cell Processor Enable register), the IRQ normally generated to indicate that a new cell was put in the RX Cell buffer is re-defined to indicate that the compare process has been complete and that the bytes that were found to be different are available for the software to access, in the link Preprocessor FIFO. For each link, the FIFO is 64 words deep to accommodate up to 64 preprocessed bytes (bytes that were found to be different). The bytes in the FIFO can be from different preprocessed cells. Whenever bit 14 of the word read from the FIFO is set, indicating the last byte of an ATM cell, the software has to check the level of bit 15 to determine if there are more bytes to be read from other processed cells on the same link. If there are no more bytes, then the software should start polling the status bit (empty/not empty) and/or wait for an IRQ before reading the FIFO. To facilitate this task, associated with the RX Cell FIFOs, the Processed RX Cell Link FIFO Status register (0x107) reports if a FIFO is empty or not empty. Each bit in the register is reflecting the status of one of the sixteen links. When the preprocessing option is not enabled, the RX Cell buffers operate the same way as in the MT90220/221. All 53 bytes from the ATM Cell are accessible when the preprocessing mode is disabled.
6.5
TDM Ring Block
The TDM Ring Block is typically used to form IMA groups that source their links from more than one ZL30226/7/8. All ZL30226/7/8 devices in the TDM Ring must operate synchronously, with the same system clock. This system clock needs to be the identical in frequency but not necessarily phase aligned. The TDM Ring is located between the TDM Serial Interface (S/P converters) and the internal Transmission Control (TC) / IMA blocks (see figures 5 and 7). This bus allows links to be routed from one ZL30226/7/8 to other ZL30226/7/8s as if the link was internally sourced, limited by the ZL30228's link capacity of 16 links (8 links on the ZL30227 and 4 links on the ZL30226) and the TDM Ring capacity of 32 links.
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Zarlink Semiconductor Inc.
ZL30226/7/8
Data Sheet
Operation of the TDM Ring is programmed via 16 Ring Tx Link (0x0181-0x0190) registers, 16 Ring Rx Link (0x01C0-0x01CF) registers and one Ring Tx Control (0x0180) register. The Ring Tx Control (0x0180) sets which ZL30226/7/8 is the master (source of the TDM Ring clock) and whether the TDM Ring is active (not tri-stated). There can be only one TDM Ring master in a single ring. A link is then placed on the ring by associating it with one available time slot and then retrieved off the ring by referencing the same time slot. See Technical Note TN90224.1 for more information.
6.6
SRAM decoding for ZL30226 and ZL30227
The SRAM decoding block has a feature that allows more efficient external SRAM memory utilization when only 8 or 4 TDM links are used. This is particularly pertinent to the ZL30227 and ZL30226. SRAM address decoding is based in part on the link number. Since the ZL30227 and ZL30226 use only even numbered links, normal decoding would result in half the memory not being used. The following method describes how to more fully utilize one external SRAM component rather than using two external SRAM components, thus achieving the same differential link delay capacity with reduced board space and cost. With only one external SRAM physically connected, set bit 0 of the SRAM Control (0x0299) register to use two banks of memory. Additionally, set bit 8 of the same register to remap SRAM Chip Select 1 (sr_cs_1) to the normally unused address line. This combination of using two logical memory banks with chip select remapping will achieve the desired efficient use of a single external SRAM component.
7.0
Register Descriptions
Throughout the following register descriptions, it should be noted that only the registers and register bits corresponding to available links are meaningful. Registers and register bits corresponding to unavailable links should be masked or otherwise ignored. The ZL30228 has links 0:15. The ZL30227 has links 0, 2, 4, 6, 8, 10, 12 and 14. The ZL30226 has links 0, 4, 8, and 12. Note: For ZL30226 groups 0, 1, 2 and 3 should be used.
7.1
Register Summary
Address (Hex) Access Type D D D D D D D D D Reset Value (Hex) 0000 0000 0000 X0000000000 00000 0000 0000 0000 0000 0000
Description UTOPIA Output Link Address Registers UTOPIA Output Group Address Registers UTOPIA Output Link PHY Enable Registers UTOPIA Output Group PHY Enable Register UTOPIA Output User Defined Byte UTOPIA Input Link Address Registers UTOPIA Input Group Address Registers UTOPIA Input Link PHY Enable Register UTOPIA Input Group PHY Enable Register
0x0000-0x0007 0x0008-0x000B 0x0010 0x0011 0x0012 0x0040-0x0047 0x0048-0x004B 0x0050 0x0051
Table 5 - Register Summary
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Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex) 0x0052 0x0053 0x0080 0x0086 0x0087 0x0088 0x0089 0x008B-0x0092 0x0093-0x0096 0x009B 0x0C0 - 0x0C7 0x00C8 0x00C9 0x00CA 0x00CC 0x00CF 0x00D9 0x00DA 0x00DB 0x00DC 0x00DD 0x00DE 0x00DF 0x00E0 0x00E1 0x00E2 0x00E3 0x00E4 0x00E5 0x00E6 0x0100 0x0101 0x0102 0x0105 0x0106 0x0107 Access Type D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D Reset Value (Hex) 000X0000000 00000 0000 000000001X0 00000 00FF 00FF 0000 0000 0101 0101 0000 0C0C 000C 0067 0091 0101 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0020 0000 0000 0000 0000 0000 0000 0000 0000 0000 Description UTOPIA Input Control Register UTOPIA Input Parity Error Register TX Cell RAM Control Register TX ICP Cell Handler Register TX IMA Frame Indication Register TX ICP Cell Interrupt Enable Register TX IMA Frame Interrupt Enable Register TX Link FIFO Length Definition Register
Data Sheet
TX IMA Group FIFO Length Definition Register TX FIFO Length Status Register RX Link Control Registers Loss of Delineation Register Cell Delineation Register IMA Frame Delineation Register User Defined RX OAM Label Register RX OIF Status Register RX OIF Counter Clear Command Register RX Wrong Filler Status Register RX Load Values/Link Select Register RX OAM Label Register RX Link IMA ID Registers RX ICP Cell Offset Register RX Link Frame Sequence Number Register RX Link SCCI Sequence Number Register RX Link OIF Counter Value Register RX Link ID Number Register RX State Register IMA Frame State Machine Status Register Cell Delineation Status Register RX Cell Type RAM Register 1 RX Cell Type RAM Register 2 RX Cell Process Enable Register RX Cell Buffer Increment Read Pointer Register RX Cell Level FIFO Status Register Processed RX Cell link FIFO Status Register
Table 5 - Register Summary (continued)
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Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex) 0x0108 0x0140 - 0x014F 0x0180 0x0181 - 0x0190 0x01C0 0x01CF 0x0201--x0208 0x0209 - 0x0210 0x0219 - 0x021C 0x0280 0x0281 0x0282 0x0283 0x0284 0x0285 0x0286 0x0287 - 0x028E 0x0297 0x0298 0x0299 0x029A - 0x02A1 0x02AA 0x02AD 0x0300 - 0x0307 0x0310 - 0x0317 0x0318 - 0x031F 0x0321 - 0x0324 0x0333 0x0336 - 0x033D 0x0345 0x0346 0x0401 0x0402 0x0403 - 0x0406 0x040B 0x040C Access Type D D D D D D D D Sync D D D Sync D D D Sync Sync D D D D D D D D D D D D D D D D D Reset Value (Hex) 0000 8000 0000 0000 0000 0000 0000 0C0C 000000001X0 00000 0000 0000 0000 0000 0004 0000 0004 0000 0000 0000 0000 0000 0000 00B0 physical link # 0808 3030 0000 physical link # 0000 FFFF 0000 0000 0C0C 0000 0000 Description ICP Cell RAM Debug Register Processed RX Cell link FIFO Register Ring Tx Control Register Ring Tx Link Registers Ring Rx Link Registers RX Recombiner Registers RX Reference Link Control Registers RX IDCR Integration Registers RX External SRAM Access Control Register Increment Delay Control Register Decrement Delay Control Register RX Recombiner Delay Control Registers RX External SRAM Read/Write Data RX Delay Register RX Delay Link Number Register RX Guardband/Delta Delay Register RX External SRAM Read/Write Address RX External SRAM Read/Write Address 1 SRAM Control Register RX Maximum Operational Delay Register RX Delay Select Register Enable Recombiner Status TX Group Control Mode Registers TX ICP Cell Offset Registers TX Link Control Registers TX IMA Control Registers TX Add Link Control Register TX Link ID Registers TX Link Active Status Register TX IMA Mode Status Register UTOPIA Input Cell Counter Groups Register UTOPIA Input Cell Counter Links Register TX IDCR Integration Registers IRQ IMA Group Overflow Enable Register
Data Sheet
RX UTOPIA IMA Group FIFO Overflow IRQ Enable Register
Table 5 - Register Summary (continued)
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Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex) 0x040D 0x040E 0x040F 0x0410 - 0x041F 0x0420 - 0x0427 0x0430 0x0431 0x0432 0x0433 0x0434 0x0435 - 0x0444 0x0445 - 0x0454 0x0455 0x0457 0x0500 to 0x05FF 0x0600 - 0x060F 0x0610 - 0x061F 0x0620 - 0x062F 0x0630 0x0631 0x0632 0x0634- 0x0635 0x0700 - 0x070F 0x0710 - 0x071F 0x0720 - 0x072F 0x0741 0x0800 - 0x0BFF Access Type D D Sync D D D D D D D D D D D D D D D D D D D D D D D D Reset Value (Hex) 2220 0000 0080 0000 0000 Sync Sync Sync 0000 0000 0000 0000 0000 0000 XXXX 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 XXXX Device ID Register General Status Register Counter Transfer Command Register IRQ Link TC Overflow Status Registers IRQ IMA Overflow Status Registers Counter Upper Byte Counter Bytes 2 and 1 Register Select Counter Register IRQ Master Enable Register IRQ Link TC Overflow Enable Register IRQ Link Status Registers IRQ Link Enable Registers IRQ Master Status Register IRQ IMA Group Overflow Status Register TX IMA ICP Cell Registers TDM TX Link Control Register TDM TX Mapping (timeslots 15:0) Register TDM TX Mapping (timeslots 31:16) Register TXCK Status Register RXCK Status Register REFCK Status Register PLL Reference Control Register TDM RX Link Control Register TDM RX Mapping (timeslots 15:0) Register TDM RX Mapping (timeslots 31:16) Register RX Automatic ATM Synchronization Register RX IMA ICP Cell Description
Data Sheet
Table 5 - Register Summary (continued)
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Zarlink Semiconductor Inc.
ZL30226/7/8
7.2 Detailed Register Description
Data Sheet
Address (Hex): Direct access Reset Value (Hex): Bit # 15:13 12:8 7:5 4:0 Type R R/W R R/W
0x000-0x007 (8 regs) 1 register per 2 links in non-IMA mode. Link 0 is paired with link 8, link 1 with link 9 and so on. 0000 Description Unused. Read all 0's. UTOPIA PHY Address of link N+8 when in non-IMA mode. Unused. Read all 0's. UTOPIA PHY Address of link N when in non-IMA mode. Table 6 - UTOPIA Output Link Address Registers
Address (Hex): Direct access Reset Value (Hex): Bit # 15:13 12:8 7:5 4:0 Type R R/W R R/W
0x0008-0x00B (4 regs) 1 reg. per 2 IMA Groups. IMA group 0 is paired with IMA group 4, IMA group 1 with IMA group 5 and so on. For ZL30226 groups 0, 1, 2 and 3 are used. 0000 Description Unused. Read all 0's. UTOPIA PHY Address of IMA Group N+4. Unused. Read all 0's. UTOPIA PHY Address of IMA Group N. Table 7 - UTOPIA Output Group Address Registers
Address (Hex): Direct access Reset Value (Hex): Bit # 15 14 ... 1 0 Type R/W R/W ... R/W R/W
0x0010 (1 reg) 1 register to enable the links in non-IMA mode. 0000 Description Enable UTOPIA PHY address of link 15. A 1 enables the PHY port Address, non-IMA mode. Enable UTOPIA PHY address of link 14. A 1 enables the PHY port Address, non-IMA mode. ... Enable UTOPIA PHY address of link 1. A 1 enables the PHY port Address, non-IMA mode. Enable UTOPIA PHY address of link 0. A 1 enables the PHY port Address, non-IMA mode. Table 8 - UTOPIA Output Link PHY Enable Registers
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Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Bin): Type 15 14 13 12 11 10 9 8 7 6 ... 1 0 R R/W R/W R/W R/W R/W R/W R/W R/W R/W ... R/W R/W Reserved. Reserved. Write 0 for normal operation. Reserved. Write 0 for normal operation. Reserved. Write 0 for normal operation.
Data Sheet
0x0011 (1 reg) 1 register to enable the IMA Groups.For ZL30226 groups 0, 1, 2 and 3 are used. X000000000000000 Description
16/8-bit mode selection bit for the RX UTOPIA data bus. When set the RX UTOPIA interface is operating in 8-bit mode, when reset it is operating in 16-bit mode. Reserved. Write 0 for normal operation. Reset UTOPIA RX state machines when set to 1. Reserved. Write 0 for normal operation. Enable UTOPIA PHY address of IMA Group 7. A 1 enables the PHY port Address. Enable UTOPIA PHY address of IMA Group 6. A 1 enables the PHY port Address. ... Enable UTOPIA PHY address of IMA Group 1. A 1 enables the PHY port Address. Enable UTOPIA PHY address of IMA Group 0. A 1 enables the PHY port Address. Table 9 - UTOPIA Output Group PHY Enable Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:12 11 10 9 8 7:0 Type R R/W R/W R/W R/W R/W
0x0012 (1 reg) 1 register which contains the User Defined Byte. This byte is inserted into the sixth byte of the header when operating in sixteen-bit mode. 0000 Description Unused. Read all 0's. Reserved. Write 0 for normal operation Reserved. Write 0 for normal operation Write 0 for normal operation, 1 to tristate parity. Parity Bit. EVEN parity is selected when this bit is set. ODD parity is selected when this bit is cleared. User Defined Byte. This byte is inserted into the sixth byte of the header when cells are being output in 16-bit mode. Table 10 - UTOPIA Output User Defined Byte
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Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:13 12:8 7:5 4:0 Type R R/W R R/W Unused. Read all 0's. UTOPIA PHY Address of Link N+8 when in non-IMA mode. Unused. Read all 0's. UTOPIA PHY Address of Link N when in non-IMA mode. Table 11 - UTOPIA Input Link Address Registers
Data Sheet
0x0040-0x0047 (8 reg) 1 register per 2 links in non-IMA mode. Link 0 is paired with link 8, link 1 with link 9 and so on. 0000 Description
Address (Hex): Direct access Reset Value (Hex): Bit # 15:13 12:8 7:5 4:0 Type R R/W R R/W
0x0048-0x004B (4 reg) 1 register per 2 IMA Groups. IMA group 0 is paired with IMA group 4, IMA group 1 with IMA group 5 and so on. For ZL30226 groups 0, 1, 2 and 3 are used. 0000 Description Unused. Read all 0's. UTOPIA PHY Address of IMA Group N+4. Unused. Read all 0's. UTOPIA PHY Address of IMA Group N. Table 12 - UTOPIA Input Group Address Registers
Address (Hex): Direct access Reset Value (Hex): Bit # 15 14 ... 1 0 Type R/W R/W ... R/W R/W
0x0050 (1 reg) 1 register to enable the links in non-IMA mode. 0000 Description Enable UTOPIA PHY address of link 15. A 1 enables the PHY port Address, non-IMA mode. Enable UTOPIA PHY address of link 14. A 1 enables the PHY port Address, non-IMA mode. ... Enable UTOPIA PHY address of link 1. A 1 enables the PHY port Address, non-IMA mode. Enable UTOPIA PHY address of link 0. A 1 enables the PHY port Address, non-IMA mode. Table 13 - UTOPIA Input Link PHY Enable Register
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Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:12 11:8 7 6 ... 1 0 Type R R/W R/W R/W ... R/W R/W Unused. Reads all 0's. Reserved. Write all 0's for normal operation.
Data Sheet
0x0051 (1 reg) 1 register to enable the IMA Groups. For ZL30226 groups 0, 1, 2 and 3 are used. 0000 Description
Enable UTOPIA PHY address of IMA Group 7. A 1 enables the PHY port Address. Enable UTOPIA PHY address of IMA Group 6. A 1 enables the PHY port Address. ... Enable UTOPIA PHY address of IMA Group 1. A 1 enables the PHY port Address. Enable UTOPIA PHY address of IMA Group 0. A 1 enables the PHY port Address. Table 14 - UTOPIA Input Group PHY Enable Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:14 13 12 11 10 Type R R R/W R/W R/W
0x0052 (1 reg) 1 register for all the UTOPIA Input ports.For ZL30226 groups 0, 1, 2 and 3 are used. 000X000000000000 Description Unused. Read all 0's. Reserved. Write 0 for normal operation. Parity Bit. The incoming Parity Bit is odd parity when 0, even parity when 1. Reserved. Write 0 for normal operation. UTOPIA loopback mode indicator. When set the Tx UTOPIA will accept cells and loop these back to the Rx UTOPIA interface. The Rx UTOPIA interface will then output these cells. Reserved. Write 0 for normal operation Reserved. Write 0 for normal operation Selects between 16- and 8-bit mode for the Utopia bus. A 0 selects a 16-bit wide bus and a 1 selects an 8-bit wide bus. A 1 resets the state of the Input UTOPIA Controller. Write 0 for normal operation. Reserved. Write 0 for normal operation. Unassigned Cell Filter. A 1 signifies that the Unassigned1 cells coming from the ATM layer will be discarded. The Unassigned/Idle cell counter is incremented for each cell discarded. Idle Cell Filter. A 1 signifies that the Idle2 cells coming from the ATM layer will be discarded. The Unassigned/Idle cell counter is incremented for each cell discarded. ATM Forum Polynomial. A 1 disables the addition of the ATM Forum Polynomial calculation on the HEC calculated as per I.432. A 0 means that the coset value is included in the HEC value. Table 15 - UTOPIA Input Control Register
9 8 7 6 5 4
R/W R/W R/W R/W R/W R/W
3 2
R/W R/W
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Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 1:0 Type R/W
Data Sheet
0x0052 (1 reg) 1 register for all the UTOPIA Input ports.For ZL30226 groups 0, 1, 2 and 3 are used. 000X000000000000 Description HEC Verification. 11: Enable HEC error correction if 1 bit is wrong, discard cell if more than 1 bit are wrong. 10: Discard cell if HEC is wrong, no HEC correction. 01: Enable HEC error correction if 1 bit is wrong, no correction if more than 1 bit wrong, cell is not discarded if HEC is wrong. 00: No verification of HEC. Table 15 - UTOPIA Input Control Register (continued)
1. Unassigned Cells have a fixed header corresponding to 00000000 00000000 00000000 0000xxx0. 2. Idle Cells have a fixed header corresponding to 00000000 00000000 00000000 00000001.
Address (Hex): Direct access Reset Value (Hex): Bit # 15 14 13 13 12 11:0 Type ROL ROL W R R/W R
0x0053 (1 reg) 1 register to contain information about parity errors on the Tx UTOPIA data bus. 0000 Description Indicates that the parity error counter has rolled-over. This is a sticky bit which is set by the hardware and reset by the user (by writing '0' to this bit). Indicates that at least one parity error has occurred since this register was reset. This is a sticky bit which is set by the hardware and reset by the user (by writing '0' to this bit. When written with a 1 the internal TX UTOPIA Parity Error Counter value will be transferred to the lower 12 bits of this register. When written with '0', no transfer is done. Reading a 1 in this register indicates that the TX UTOPIA Parity Error Counter has been updated. Reading a 0 indicates that the register is not updated yet. When this bit is set the TX UTOPIA Parity Error Counter will be reset. When this bit is reset the TX UTOPIA Parity Error Counter will operate normally. TX UTOPIA Parity Error Counter. These bits contain the value of the TX UTOPIA Parity Error Counter. The counter must be loaded into the register using bit 13. Table 16 - UTOPIA Input Parity Error Register
Address (Hex): Direct access Reset Value (Bin): Bit # 15:8 7 6 5 4:1 0 Type R R R/W R/W R/W R/W
0x0080 (1 reg) Used for initialization of the internal TX Internal Cell RAM (Filler, Idle Cells, etc.) 000000001X000000 Description Unused. Read all 0's. Status Bit. Goes to 0 during initialization and returns to 1 on completion of initialization. Write 1 to this bit for normal operation. Write 0 in conjunction with bit 0 to initialize the TX Cell RAM; otherwise, write 1. Reserved. Write 0 for normal operation. Reserved. Write 0's for normal operation. Reserved. Write 0 to initialize the internal Cell RAM. Table 17 - TX Cell RAM Control Register
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Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 7 Type R R/W Unused. Read all 0's.
Data Sheet
0x0086 (1 reg) Controls the transfer of TX ICP cells. For ZL30226 groups 0, 1, 2 and 3 are used. 00FF Description Write 0 to initiate the transfer of the TX ICP cell from the TX ICP Cell Memory to the internal memory for the IMA group 7. The bit reads '0' until the transfer is complete, the bit reads '1'. Write a '1' has no effect. Write 0 to initiate the transfer of the TX ICP cell from the TX ICP Cell Memory to the internal memory for the IMA group 6. The bit reads '0' until the transfer is complete, the bit reads '1'. Write a '1' has no effect. ... Write 0 to initiate the transfer of the TX ICP cell from the TX ICP Cell Memory to the internal memory for the IMA group 1. The bit reads '0' until the transfer is complete, the bit reads '1'. Write a '1' has no effect. Write 0 to initiate the transfer of the TX ICP cell from the TX ICP Cell Memory to the internal memory for the IMA group 0. The bit reads '0' until the transfer is complete, the bit reads '1'. Write a '1' has no effect. Table 18 - TX ICP Cell Handler Register
6
R/W
... 1
... R/W
0
R/W
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 7 Type R R/W
0x0087 (1 reg) Indicates the beginning of the Frame on the Ref Link. 00FF Description Unused. Read all 0's. Write 0 to detect when an ICP cell is sent on the Reference link for the IMA group 7. The bit reads '0' until an ICP cell is sent on the Ref. link, then it reads '1'. Write a '1' has no effect. Write 0 to detect when an ICP cell is sent on the Reference link for the IMA group 6. The bit reads '0' until an ICP cell is sent on the Ref. link, then it reads '1'. Write a '1' has no effect. ... Write 0 to detect when an ICP cell is sent on the Reference link for the IMA group 1. The bit reads '0' until an ICP cell is sent on the Ref. link, then it reads '1'. Write a '1' has no effect. Write 0 to detect when an ICP cell is sent on the Reference link for the IMA group 0. The bit reads '0' until an ICP cell is sent on the Ref. link, then it reads '1'. Write a '1' has no effect. Table 19 - TX IMA Frame Indication Register
6
R/W
... 1
... R/W
0
R/W
78
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 7 6 ... 1 0 Type R R/W R/W ... R/W R/W Unused. Read all 0's. 0x0088 (1 reg) Interrupt Enable register for the TX ICP Handler register. 0000 Description
Data Sheet
Write a 1 will enable the generation of an interrupt when the transfer of the TX ICP cell for the IMA Group 7 is completed. A 0 will inhibit the generation of an interrupt. Write a 1 will enable the generation of an interrupt when the transfer of the TX ICP cell for the IMA Group 6 is completed. A 0 will inhibit the generation of an interrupt. .... Write a 1 will enable the generation of an interrupt when the transfer of the TX ICP cell for the IMA Group 1 is completed. A 0 will inhibit the generation of an interrupt. Write a 1 will enable the generation of an interrupt when the transfer of the TX ICP cell for the IMA Group 0 is completed. A 0 will inhibit the generation of an interrupt. Table 20 - TX ICP Cell Interrupt Enable Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 7 6 ... 1 0 Type R R/W R/W ... R/W R/W
0x0089 (1 reg) Interrupt Enable register for the TX ICP Handler register. 0000 Description Unused. Read all 0's. Write a 1 will enable the generation of an interrupt from the frame indication for IMA Group 7. A 0 will inhibit the generation of an interrupt. Write a 1 will enable the generation of an interrupt from the frame indication for IMA Group 6. A 0 will inhibit the generation of an interrupt. .... Write a 1 will enable the generation of an interrupt from the frame indication for IMA Group 1. A 0 will inhibit the generation of an interrupt. Write a 1 will enable the generation of an interrupt from the frame indication for IMA Group 0. A 0 will inhibit the generation of an interrupt. Table 21 - TX IMA Frame Interrupt Enable Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:12 11:8 7:4 3:0 Type R R/W R/W R/W
0x008B-0x0092 (8 reg) 1 register per 2 links. Link 0 is paired with link 8, link 1 is paired with link 9 and so on. 0101 Description Unused. Read 0's. TX FIFO Length Link N+8. Reserved. Write 0's for normal operation. TX FIFO Length Link N. Table 22 - TX Link FIFO Length Definition Register
79
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:12 11:8 7:4 3:0 Type R/W R/W R/W R/W Unused. Read 0's. TX FIFO Length IMA Group N+4. Reserved. Write 0's for normal operation. TX FIFO Length IMA Group N. Table 23 - TX IMA Group FIFO Length Definition Register
Data Sheet
0x0093-0x0096 (4 reg) 1 register per 2 IMA groups. Group 0 is paired with Group 4, Group 1 is paired with Group 5 and so on.For ZL30226 groups 0, 1, 2, 3 are used. 0101 Description
Address (Hex): Direct access Reset Value (Hex): Bit # 15:7 6:0 5:0 Type R R W
0x009B (1 reg) 0000 Description Unused. Read 0's. 6:0 contains FIFO Length Free Cells 4:0 contains FIFO Length of IMA Groups and Links Selects FIFO: 000000 - 001111: selects Link FIFO 010000 - 010111: selects IMA FIFO 011000: selects Free Cell FIFO 100000 - 101111: selects ICP Cell Modifier length LINK FIFO Table 24 - TX FIFO Length Status Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15 14 13 12 11 10 Type R/W R/W R/W R/W R/W R/W
0x00C0 - 0x00C7 (8 reg) 1 register per 2 links. Link 0 is paired with link 8, link 1 with link 9 and so on. 0C0C Description A value of 1 means that all cells are counted for the link N+8. A value of 0 means that all stuff cells are counted for the link N+8. A value of 1 enables the IMA mode for the link N+8. A value of 0 enables the non-IMA mode for the link N+8. A value of 1 enables the descrambling of the cell for the link N+8. When set to 1, count all USER cells for link N+8, when cleared to 0, count Filler/Idle/Unassigned cells for link N+8. A value of 1 means that the Unassigned and Idle cells are discarded upon reception for the link N+8. A value of 1 enables the discard option of the cells with wrong HEC. A value of 0 will disables the discard option, all the cells will be written to the receive buffer. Table 25 - RX Link Control Registers
80
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 9 Type R/W
Data Sheet
0x00C0 - 0x00C7 (8 reg) 1 register per 2 links. Link 0 is paired with link 8, link 1 with link 9 and so on. 0C0C Description A value of 1signifies that the ATM Forum polynomial value (coset) is not to be added to the HEC before the verification. A value of 0 means that the HEC is calculated and compared (i.e. including the coset). A value of 1 enables the correction of the cells with a wrong HEC. A value of 0 disable the correction of the HEC. A value of 1 means that all cells are counted for the link N. A value of 0 means that all stuff cells are counted for the link N. A value of 1 enables the IMA mode for this link. A value of 0 enables the non-IMA mode for the link N. A value of 1 enables the descrambling of the cell for the link N. When set to 1, count all USER cells for link N, when cleared to 0, count Filler/Idle/Unassigned cells for link N. A value of 1 means that the Unassigned and Idle cells are discarded upon reception for the link N. A value of 1 enables the discard option of the cells with wrong HEC. A value of 0 will disables the discard option, all the cells will be written to the receive buffer. A value of 1signifies that the ATM Forum polynomial value (coset) is not to be added to the HEC before the verification. A value of 0 means that the HEC as per ATM Forum is calculated and compared (i.e. including the coset). A value of 1 enables the correction of the cells with a wrong HEC. A value of 0 disable the correction of the HEC. Table 25 - RX Link Control Registers (continued)
8 7 6 5 4 3 2 1
R/W R/W R/W R/W R/W R/W R/W R/W
0
R/W
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 7:0 Type R R/W
0x00C8 (1 reg) 1 reg. for all 16 cell delineation state machines 000C Description Unused. Read all 0's. Contains the number of consecutive cell periods that the CD circuit will count before the incoming ATM cell stream to be considered in LCD state. Each count will be done on a cell by cell basis. The value of this register is multiplied by 2 before being loaded in the internal counter. (The internal counter value can be from 2 to 510).
Note that a value of 0 is not allowed as an LCD condition would be generated.
Table 26 - Loss of Delineation Register
81
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 7:4 Type R R/W Unused, Read all 0's. 0x00C9 (1 reg) 1 register for all 16 cell delineation state machines. 0067 Description
Data Sheet
DELTA parameter value for the Cell Delineation register. The number of consecutive cells with correct HEC to leave the PRESYNC state to go to the SYNC state. The default value is 6. ALPHA parameter value for the Cell Delineation register. The number of consecutive cells with incorrect HEC to leave the SYNC state to go to the HUNT state. The default value is 7. Table 27 - Cell Delineation Register
3:0
R/W
Address (Hex): Direct access Reset Value (Hex): Bit # 15:9 8 7:6 Type R R/W R/W
0x00CA (1 reg) 1 reg. for all 8 IMA Frame state machines. 0091 Description Unused. Read all 0's. Reserved. Write 0 for normal operation. ALPHA parameter value for the IMA Frame Delineation.state machine. The number of consecutive invalid ICP cells to leave the IMA SYNC state to go to the IMA HUNT state.The default value is 2. BETA parameter value for the Cell Delineation.state machine. The number of consecutive errored ICP cells to leave the IMA SYNC state to go to the IMA HUNT state. The default value is 2. GAMMA parameter value for the Frame Delineation state machine. The number of consecutive valid ICP cells to leave the IMA PRESYNC state to go to the IMA SYNC state. The default value is 1. Table 28 - IMA Frame Delineation Register
5:3
R/W
2:0
R/W
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 7:0 Type R/W R/W
0x00CC - 0x00CF (4 reg) 1 reg. per 2 IMA Groups. IMA Group 0 is paired with IMA Group 4 and so on. For ZL30226 groups 0,1,2 and 3 are used. 0101 Description RX OAM Label for IMA Group N+4. RX OAM Label for IMA Group N. Table 29 - User Defined RX OAM Label Register
82
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15 14 ... 1 0 Type R/W R/W ... R/W R/W 0x00D9 (1 reg) 1 register for the 16 RX links. 0000 Description An OIF state was detected on the physical link 15. Cleared by writing a 0. An OIF state was detected on the physical link 14. Cleared by writing a 0. ... An OIF state was detected on the physical link 1. Cleared by writing a 0. An OIF state was detected on the physical link 0. Cleared by writing a 0. Table 30 - RX OIF Status Register
Data Sheet
Address (Hex): Direct access Reset Value (Hex): Bit # 15 14 ... 1 0 Type R/W R/W ... R/W R/W
0x00DA (1 reg) 1 register for the 16 RX links. 0000 Description Write a 0 to clear the OIF counter for physical link 15. Write a 0 to clear the OIF counter for physical link 14. ... Write a 0 to clear the OIF counter for physical link 1. Write a 0 to clear the OIF counter for physical link 0. Table 31 - RX OIF Counter Clear Command Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15 14 ... 1 0 Type R/W R/W ... R/W R/W
0x00DB (1 reg) 1 register for the 16 RX links. 0000 Description Set to 1 to indicate that at least 1 Filler cell with a wrong CRC was received on link 15. The bit is reset by writing 0 to it. Set to 1 to indicate that at least 1 Filler cell with a wrong CRC was received on link 14. The bit is reset by writing 0 to it. ... Set to 1 to indicate that at least 1 Filler cell with a wrong CRC was received on link 1. The bit is reset by writing 0 to it. Set to 1 to indicate that at least 1 Filler cell with a wrong CRC was received on link 0. The bit is reset by writing 0 to it. Table 32 - RX Wrong Filler Status Register
83
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:5 4 3:0 Type R R R/W Unused. Read all 0's. This bit toggles after every write to the ZL30226/7/8 device.
Data Sheet
0x00DC (1 reg) 1 register to select the link from which to extract the RX ICP cells values shown in following registers. 0000 Description
Selects the RX physical link number to update the values from the RX ICP cell. This is typically used when the RX Link is enabled but in non-IMA mode to collect the values received over the ICP cells. Table 33 - RX Load Values/Link Select Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 7:0 Type R R
0x00DD (1 reg) The value is updated on completion of the write action in the RX Load Values register. 0000 Description Unused. read all 0's. This register stores the value of the RX OAM label value extracted from the valid RX ICP cell received on the link selected in the RX Load Values/Link Select register. Table 34 - RX OAM Label Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 7:0 Type R R
0x00DE (1 reg) The value is updated on completion of the write action in the RX Load Values register. 0000 Description Unused. Read all 0's. This register stores the value of the IMA ID extracted from the valid RX ICP cell received on the link selected in the RX Load Values/Link Select register. Table 35 - RX Link IMA ID Registers
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 Type R
0x00DF (1 reg) The value is updated on completion of the write action in the RX Load Values register. 0000 Description Unused. Read all 0's. Table 36 - RX ICP Cell Offset Register
84
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 7:0 Type R
Data Sheet
0x00DF (1 reg) The value is updated on completion of the write action in the RX Load Values register. 0000 Description Defines the ICP cell offset of the link selected in the RX Load Values/Link Select register. The significant bits are used depending on the value of M. M = 256; bits 7-0 are used, M = 128; bits 6-0 are used; M = 64; bits 5-0 are used; M = 32; bits 4-0 are used. Table 36 - RX ICP Cell Offset Register (continued)
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 7:0 Type R R
0x00E0 (1 reg) The value is updated on completion of the write action in the RX Load Values register. 0001 Description Unused. Read all 0's. This register reports the IMA Frame sequence number as reported in the last received valid ICP cell of the selected link. Table 37 - RX Link Frame Sequence Number Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 7:0 Type R R
0x00E1 (1 reg) The value is updated on completion of the write action in the RX Load Values register. 0000 Description Unused. Read all 0's. This register reports the SCCI sequence number as reported in the last received valid ICP cell of the link selected in the RX Load Values/Link Select register. Table 38 - RX Link SCCI Sequence Number Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 7:0 Type R R
0x00E2 (1 reg) The value is updated on completion of the write action in the RX Load Values register. 0000 Description Unused. Read all 0's. Content of the OIF counter for the link selected in the RX Load Values/Link Select register. Table 39 - RX Link OIF Counter Value Register
85
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 7 6 5 4:0 Type R R R R R Unused. Read all 0's. LIF state of the link selected in the RX Load Values/Link Select register. LCD state of the link selected in the RX Load Values/Link Select register.
Data Sheet
0x00E3 (1 reg) The value is updated on completion of the write action in the RX Load Values register. 0020 Description
A value of 1 means that the link selected in the RX Load Values/Link Select register is a reference link for his IMA Group. These bits report the link ID number for the link selected in the RX Load Values/Link Select register. Table 40 - RX Link ID Number Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:6 5:4 3:2 Type R R R
0x00E4 (1 reg) The value is updated on completion of the write action in the RX Load Values register. 0000 Description Unused. Read all 0's. Frame length (value of M) of the link selected in the RX Load Values/Link Select register. IMA Frame State: 00: Hunt 01: Presync 10: Sync. 11: Stuffed Frame event. Cell Delineation State: 00: Hunt 01: Presync 10: Sync. 11: Unused. Table 41 - RX State Register
1:0
R
Address (Hex): Direct access Reset Value (Hex): Bit # 15 Type R
0x00E5 (1 reg) 1 register for all links. 0000 Description A 1 indicates that the IMA Frame State Machine (IFSM) for the link 15 is in Synchronized State. A 0 indicates that the IFSM for the link 15 is in not in the Synchronized State. This bit is not latched and is reflecting the current state of the IFSM. Table 42 - IMA Frame State Machine Status Register
86
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 14 Type R 0x00E5 (1 reg) 1 register for all links. 0000 Description
Data Sheet
A 1 indicates that the IMA Frame State Machine (IFSM) for the link 14 is in Synchronized State. A 0 indicates that the IFSM for the link 14 is in not in the Synchronized State. This bit is not latched and is reflecting the current state of the IFSM. ... A 1 indicates that the IMA Frame State Machine (IFSM) for the link 1 is in Synchronized State. A 0 indicates that the IFSM for the link 1 is in not in the Synchronized State. This bit is not latched and is reflecting the current state of the IFSM. A 1 indicates that the IMA Frame State Machine (IFSM) for the link 0 is in Synchronized State. A 0 indicates that the IFSM for the link 0 is in not in the Synchronized State. This bit is not latched and is reflecting the current state of the IFSM. Table 42 - IMA Frame State Machine Status Register (continued)
... 1
... R
0
R
Address (Hex): Direct access Reset Value (Hex): Bit # 15 Type R
0x00E6 (1 reg) 1 register for all links. 0000 Description A 1 indicates that the Cell Delineation State Machine (CD) for the link 15 is in Synchronized State. A 0 indicates that the CD for the link 15 is in not in the Synchronized State. This bit is not latched and is reflecting the current state of the CD. A 1 indicates that the Cell Delineation State Machine (CD) for the link 14 is in Synchronized State. A 0 indicates that the CD for the link 14 is in not in the Synchronized State. This bit is not latched and is reflecting the current state of the CD. ... A 1 indicates that the Cell Delineation State Machine (CD) for the link 1 is in Synchronized State. A 0 indicates that the CD for the link 1 is in not in the Synchronized State. This bit is not latched and is reflecting the current state of the CD. A 1 indicates that the Cell Delineation State Machine (CD) for the link 0 is in Synchronized State. A 0 indicates that the CD for the link 0 is in not in the Synchronized State. This bit is not latched and is reflecting the current state of the CD. Table 43 - Cell Delineation Status Register
14
R
... 1
... R
0
R
87
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:14 Type R/W 0x0100 (1 reg) Access for RX link 7, 6, 5, 4, 3, 2, 1, 0 0000 Description
Data Sheet
These 2 bits select the type of cells stored in the RX ICP Cell buffer for physical link 7 00: valid RX ICP Cells with changes. 01: All valid RX ICP Cells. 10: All valid RX Cells. 11: No cell written into RX buffer. These 2 bits select the type of cells stored in the RX ICP Cell buffer for physical link 6. 00: valid RX ICP Cells with changes. 01: All valid RX ICP Cells. 10: All valid RX Cells. 11: No cell written into RX buffer. ... These 2 bits select the type of cells stored in the RX ICP Cell buffer for physical link 1. 00: valid RX ICP Cells with changes. 01: All valid RX ICP Cells. 10: All valid RX Cells. 11: No cell written into RX buffer. These 2 bits select the type of cells stored in the RX ICP Cell buffer for physical link 0. 00: valid RX ICP Cells with changes. 01: All valid RX ICP Cells. 10: All valid RX Cells. 11: No cell written into RX buffer. Table 44 - RX Cell Type RAM Register I
13:12
R/W
... 3:2
... R/W
1:0
R/W
Address (Hex): Direct access Reset Value (Hex): Bit # 15:14 Type R/W
0x0101 (1 reg) Access for RX link 15, 14, 13, 12, 11, 10, 9, 8. 0000 Description These 2 bits select the type of cells stored in the RX ICP Cell buffer for physical link 15. 00: valid RX ICP Cells with changes. 01: All valid RX ICP Cells. 10: All valid RX Cells. 11: No cell written into RX buffer. These 2 bits select the type of cells stored in the RX ICP Cell buffer for physical link 14. 00: valid RX ICP Cells with changes. 01: All valid RX ICP Cells. 10: All valid RX Cells. 11: No cell written into RX buffer. ... Table 45 - RX Cell Type RAM Register 2
13:12
R/W
...
...
88
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 3:2 Type R/W 0x0101 (1 reg) Access for RX link 15, 14, 13, 12, 11, 10, 9, 8. 0000 Description
Data Sheet
These 2 bits select the type of cells stored in the RX ICP Cell buffer for physical link 9. 00: valid RX ICP Cells with changes. 01: All valid RX ICP Cells. 10: All valid RX Cells. 11: No cell written into RX buffer. These 2 bits select the type of cells stored in the RX ICP Cell buffer for physical link 8. 00: valid RX ICP Cells with changes. 01: All valid RX ICP Cells. 10: All valid RX Cells. 11: No cell written into RX buffer. Table 45 - RX Cell Type RAM Register 2 (continued)
1:0
R/W
Address (Hex): Direct access Reset Value (Hex): Bit # 15:0 Type R/W
0x0102 (1 reg) 1 bit per RX Links. 0000 Description When a bit is set to 1, the corresponding new cell placed in the RX ICP Cell FIFO is pre-processed to determine which byte(s) were changed when compared to the previous cell placed in the RX ICP buffer. When a bit is set to 0, it means that no pre-processing is to take place. Table 46 - RX Cell Process Enable Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15 14 ... 1 0 Type W W ... W W
0x0105 (1 reg) 1 reg. for all 16 RX link FIFO. 0000 Description A value of 1 will increment the position of the read pointer for the physical link 15. A 0 has no effect. A value of 1 will increment the position of the read pointer for the physical link 14. A 0 has no effect. ... A value of 1 will increment the position of the read pointer for the physical link 1. A 0 has no effect. A value of 1 will increment the position of the read pointer for the physical link 0. A 0 has no effect. Table 47 - RX Cell Buffer Increment Read Pointer Register
89
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:6 5:4 3:2 1:0 3:0 Type R R R R W Unused. Read all 0's. Level of RX ICP Cell FIFO. FIFO write pointer position. FIFO read pointer position. Select link number for FIFO Status. Table 48 - RX Cell Level FIFO Status Register
Data Sheet
0x0106 (1 reg) Write to bit 3:0 of this register to select the specific link RX ICP Cell FIFO. The value is immediately updated for a read. 0000 Description
Address (Hex): Direct access Reset Value (Hex): Bit # 15 Type R
0x0107 (1 reg) 1 register for all links. 0000 Description A 1 indicates that the preprocessing FIFO for the link 15 is not empty and it contains information to be processed by the software. A 0 indicates that the preprocessing FIFO for the link 15 is empty and does not contain any new information. A 1 indicates that the preprocessing FIFO for the link 14 is not empty and it contains information to be processed by the software. A 0 indicates that the preprocessing FIFO for the link 14 is empty and does not contain any new information. ... A 1 indicates that the preprocessing FIFO for the link 1 is not empty and it contains information to be processed by the software. A 0 indicates that the preprocessing FIFO for the link 1 is empty and does not contain any new information. A 1 indicates that the preprocessing FIFO for the link 0 is not empty and it contains information to be processed by the software. A 0 indicates that the preprocessing FIFO for the link 0 is empty and does not contain any new information. Table 49 - Processor RX Cell Link FIFO Status Register
14
R
... 1
... R
0
R
90
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:6 5:2 1 0 Type R R/W R/W R/W Unused. Always 0. Reserved. Write 0. 0: Compare entire cell. 1: Compare entire ICP cell. 0: Global debugging disabled. 1: Global debugging enabled. Table 50 - ICP Cell RAM DEBUG Register 0x0108 1 register for debug. 0000 Description
Data Sheet
Address (Hex): Direct access Reset Value (Hex): Bit # 15 Type R
0x0140 - 0x014F (16 reg) 1 register per RX Link pre-processed FIFO links. 8000 Description A 0 indicates that this word contains the last byte in the RX Cell processed FIFO for the current link. A 1 indicates that there is more bytes that were processed. A 1 indicates that this word contains the last byte from the RX Cell that was processed. A 0 indicates that there is more bytes that were processed from the same cell. Cell Offset for the byte found to be different (number range between 1 and 53). Byte content found to be different from the last received Cell. Table 51 - Processed RX Cell link FIFO Register
14 13:8 7:0
R R R
Address (Hex): Direct access Reset Value (Hex): Bit # 15:3 2 Type R R/W
0x0180 (1 reg) 1 register for TDM Ring Tx. 0000 Description Unused. Read all 0's. Ring Enable: 0: RING is NOT used and the output tri-state buffers are disabled (High Z mode). 1: RING is used and the output tri-state buffers are enabled (active). Ring Initialization: Valid only for Ring Master 0: RUN mode. 1: INITIALIZATION mode. The MASTER device generates empty HEADER bytes to initialize the RING. Ring Master 0: This device is not the MASTER of the RING. 1: This device is the MASTER of the RING (Only 1 device can be MASTER on a RING) Table 52 - Ring Tx Control Register
1
R/W
0
R/W
91
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:12 11 Type R R/W Unused. Read 0. 0x0181 - 0x0190 (16 reg) 1 register per Tx Link. 0000 Description
Data Sheet
ATM side: 0: Normal mode. The external RING is not connected to the ICP Cell Modifier. 1: RING mode. The external RING is connected to the ICP Cell Modifier. Tx Link Ring Address assigned to the ATM mode switch. TDM side: 0: Normal mode. The external RING is not connected to the TDM Tx Interface. 1: RING mode. The external RING is connected to the TDM Tx Interface. Tx Link Ring Address assigned to the TDM mode switch. Table 53 - Ring Tx Link Registers
10:6 5
R/W R/W
4:0
R/W
Address (Hex): Direct access Reset Value (Hex): Bit # 15:12 11 Type R R/W
0x01C0 - 0x01CF (16 reg) 1 register per Rx Link. 0000 Description Unused. Read 0. ATM side: 0: Normal mode. The external RING is not connected to the Rx Link Group. 1: RING mode. The external RING is connected to the Rx Link Group. Rx Link Ring Address assigned to the ATM mode switch. TDM side: 0: Normal mode. The external RING is not connected to the TDM Rx Interface. 1: RING mode. The external RING is connected to the TDM Rx Interface. Rx Link Ring Address assigned to the TDM mode switch. Table 54 - Ring Rx Link Registers
10:6 5
R/W R/W
4:0
R/W
Address (Hex): Direct access Reset Value (Hex): Bit # 15:13 12 11 Type R R/W R/W
0x0201-0x0208 (8 reg) 1 register per 2 RX link. Link 0 is paired with link 8, link 1 with link 9 and so on. For ZL30226 groups 0, 1, 2 and 3 are used. 0000 Description Unused. Read all 0's. Recombiner Control: 1 to enable the recombiner and a 0 to disable. This bit works in conjunction with the RX Recombiner Delay register. Reserved: write '0'. Table 55 - RX Recombiner Registers
92
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 10:8 Type R/W
Data Sheet
0x0201-0x0208 (8 reg) 1 register per 2 RX link. Link 0 is paired with link 8, link 1 with link 9 and so on. For ZL30226 groups 0, 1, 2 and 3 are used. 0000 Description These 3 bits specify which IMA Group the link N+8 belongs to: 000: IMA Group #0 001: IMA Group #1 010: IMA Group #2 011: IMA Group #3 100: IMA Group #4 101: IMA Group #5 110: IMA Group #6 111: IMA Group #7 Reserved: write '0'. Recombiner Control: 1 to enable the recombiner and a 0 to disable. This bit works in conjunction with the RX Recombiner Delay register. Reserved: write '0'. These 3 bits specify which IMA Group N the link belongs to: 000: IMA Group #0 001: IMA Group #1 010: IMA Group #2 011: IMA Group #3 100: IMA Group #4 101: IMA Group #5 110: IMA Group #6 111: IMA Group #7 Table 55 - RX Recombiner Registers (continued)
7:5 4 3 2:0
R/W R/W R/W R/W
Address (Hex): Direct access Reset Value (Hex): Bit # 15:9 8:5 4 3:0 Type R R R/W R/W
0x0209 - 0x0210 (8 reg) 1 register per IMA Group. 0000 Description Unused. Read 0. Reserved. Value may vary. When set to 1, it enables the automatic selection of the Reference link for the Group N. When 0, the link specified in bits 3-0 is used as the reference link. These 4 bits specify which physical link is to be used as the reference link for the IMA Group N. Table 56 - RX Reference Link Control Registers
93
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:12 11:8 Type R R/W Unused. Read all 0's. Defines the integration period for an IMA Group n+4 1111: Reserved. Do not use. 1110: 222 clock cycles 1101: 221 clock cycles ... 0001: 209 clock cycles 0000: 208 clock cycles Reserved. Write all 0's. Defines the integration period for an IMA Group N 1111: Reserved. Do not use. 1110: 222 clock cycles 1101: 221 clock cycles 1100: 220 clock cycles (preferred value for SHDSL E1 service) 1011: 219 clock cycles (preferred value for SHDSL T1 service) 1010: 218 clock cycles 1001: 217 clock cycles 1000: 216 clock cycles 0111: 215 clock cycles 0110: 214 clock cycles 0101: 213 clock cycles 0100: 212 clock cycles 0011: 211 clock cycles 0010: 210 clock cycles 0001: 209 clock cycles 0000: 208 clock cycles Table 57 - RX IDCR Integration Registers
Data Sheet
0x0219 - 0x021C (4 reg) 1 register per 2 IMA groups. IMA Group 0 is paired with IMA group 4 and so on. For ZL30226 groups 0, 1, 2 and 3 are used. 0C0C Description
7:4 3:0
R/W R/W
Address (Hex): 0x0280 (1 reg) Synchronized access Reset Value (Bin: 000000001X000000 Bit # 15:8 7 6 5 4:3 2 Type R R R R/W R/W R/W Unused. Read all 0's. Upon a write to this register, the bit will go to 0 and will return to 1 when the transfer is completed. Toggle Bit. Changes its state after each rising edge of the bit 7 (ready bit). Write 0 to initiate a transfer from the ZL30226/7/8 registers to the external RAM. Write 1 to initiate a transfer from the external RAM to the ZL30226/7/8 registers. Unused. Read all 0's. Reserved. Write 0 for normal operation. Table 58 - RX External SRAM Access Control Register Description
94
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): 0x0280 (1 reg) Synchronized access Reset Value (Bin: 000000001X000000 Bit # 1:0 Type R/W Description
Data Sheet
When bit 1 is 1, there is no access to the external RAM (no reset or read or write action done). When bit 1 is 0 and bit 0 is 0, then the external RAM is initialized. When bit 1 is 0 and bit 0 is 1, then a read or write access to the external RAM is performed, as defined by bit 5. Table 58 - RX External SRAM Access Control Register (continued)
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 7 ... 2 1 0 Type R R/W ... R/W R/W R/W
0x0281 (1 reg) Used to increment the recombiner delay for an IMA Group. The value is in the Guardband/Delta Delay register 0000 Description Unused. Read all 0's. Write a 1 to increment the recombiner delay of IMA Group #7. The bit will return to 0 when the delay is adjusted. Writing a 0 has no effect. ... Write a 1 to increment the recombiner delay of IMA Group #2. The bit will return to 0 when the delay is adjusted. Writing a 0 has no effect. Write a 1 to increment the recombiner delay of IMA Group #1. The bit will return to 0 when the delay is adjusted. Writing a 0 has no effect. Write a 1 to increment the recombiner delay of IMA Group #0. The bit will return to 0 when the delay is adjusted. Writing a 0 has no effect. Table 59 - Increment Delay Control Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 7 ... 2 1 Type R R/W ... R/W R/W
0x0282 (1 reg) Used to decrement the recombiner delay for an IMA Group. The value is in the Guardband/Delta Delay register. 0000 Description Unused. Read all 0's. Write a 1 to decrement the recombiner delay of IMA Group #7. The bit will return to 0 when the delay is adjusted. Writing a 0 has no effect. ... Write a 1 to decrement the recombiner delay of IMA Group #2. The bit will return to 0 when the delay is adjusted. Writing a 0 has no effect. Write a 1 to decrement the recombiner delay of IMA Group #1. The bit will return to 0 when the delay is adjusted. Writing a 0 has no effect. Table 60 - Decrement Delay Control Register
95
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 0 Type R/W 0x0282 (1 reg) Used to decrement the recombiner delay for an IMA Group. The value is in the Guardband/Delta Delay register. 0000 Description
Data Sheet
Write a 1 to decrement the recombiner delay of IMA Group #0. The bit will return to 0 when the delay is adjusted. Writing a 0 has no effect. Table 60 - Decrement Delay Control Register (continued)
Address (Hex): Direct access Reset Value (Hex): Bit # 15 Type R/W
0x0283 (1 reg) 1 register for all links. Note: the first link of a group SHALL NOT be enabled in delayed recombination mode. 0000 Description A 1 enables the circuitry to wait for the first User cell to be received before adding the link 15 to the recombiner process. A 0 will include the link 15 in the recombiner as soon as it is enabled in the RX Recombiner register. A 1 enables the circuitry to wait for the first User cell to be received before adding the link 14 to the recombiner process. A 0 will include the link 14 in the recombiner as soon as it is enabled in the RX Recombiner register. ... A 1 enables the circuitry to wait for the first User cell to be received before adding the link 1 to the recombiner process. A 0 will include the link 1 in the recombiner as soon as it is enabled in the RX Recombiner register. A 1 enables the circuitry to wait for the first User cell to be received before adding the link 0 to the recombiner process. A 0 will include the link 0 in the recombiner as soon as it is enabled in the RX Recombiner register. Table 61 - RX Recombiner Delay Control Registers
14
R/W
... 1
... R/W
0
R/W
Address (Hex): 0x0284 (1 reg) Synchronized access Set address before the transfer is initiated with the RX External SRAM Control register. Reset Value (Hex): 0000 Bit # 15:8 7:0 Type R R/W Unused. Read all 0's. RX External SRAM Read/Write data register. Table 62 - RX External SRAM Read/Write Data Description
96
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:11 10:0 Type R R Sign bits (same value as bit 10). Delay Value. Table 63 - RX Delay Register
Data Sheet
0x0285 (1 reg) This register contains the delay value (in number of cells) selected by the RX Delay Select Register. The value always include the current guardband delay. 0004 Description
Address (Hex): Direct access Reset Value (Hex): Bit # 15:9 8 7 6 5 4 3:0 Type R R/W R/W R/W R/W R/W R
0x0286 (1 reg) This register contains the link number associated with the RX Delay value Register. 0000 Description Unused. Read all 0's. Reserved. Write 0 for normal operation. Reserved. Write 0 for normal operation. Reserved. Write 0 for normal operation. Set to 1 to enable uP access to the External SRAM, for test purposes. Clear to 0 for normal operation. Reserved. Write 0 for normal operation. Number of the physical link associated with the value in the RX Delay register. This value is not valid when reading the Maximum Delay over time. Table 64 - RX Delay Link Number Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:14 13:0 Type R R/W
0x0287 - 0x028E (8 reg) 1 value for each IMA Group to use for start-up and adding/removing delay (value in number of cells). 0004 Description Unused. Read all 0's. Guardband delay value on startup of an IMA Group or Delay value to add or substract when IMA Group is operational. Table 65 - RX Guardband/Delta Delay Register
97
Zarlink Semiconductor Inc.
ZL30226/7/8
Data Sheet
Address (Hex): 0x0297 (1 reg) Synchronized access Set address before the transfer is initiated with the RX External SRAM Control register. Reset Value (Hex): 0000 Bit # 15:4 3:0 Type R R/W Unused. Read all 0's. RX External SRAM Read/Write Address bit 19:16. Table 66 - RX External SRAM Read/Write Address Description
Address (Hex): 0x0298 (1 reg) Synchronized access Set address before the transfer is initiated with the RX External SRAM Control register. Reset Value (Hex): 0000 Bit # 15:0 Type R/W Description RX External SRAM Read/Write Address bit 15:0. Table 67 - RX External SRAM Read/Write Address 1
Address (Hex): Direct access Reset Value (Hex): Bit # 15:9 8 7 6 5 4:3 2:0 Type R R/W R/W R/W R/W R/W R/W
0x0299 (1 reg) Defines the external SRAM configuration. 0000 Description Unused, Read all 0's. Write a 1 for ZL30226/227 memory optimization2. 0 means normal operation. Write a 1 to reset the receiver1. 0 means no action. Write a 1 to reset the transmitter1. 0 means no action. Write a 1 to reset counters1. Write 0 for normal operation. Write 00 for normal operation. These 3 bits define the size of the external receive memory: 111: Reserved 110: Reserved 101: 2 banks of 512 K x 8 bits 100: 1 bank of 512 K x 8 bits 011: 2 banks of 128 K x 8 bits 010: 1 bank of 128 K x 8 bits 001: 2 banks of 32 K x 8bits 000: 1 bank of 32 K x 8 bits Table 68 - SRAM Control Register
Note 1: A software global reset of the entire ZL30226/7/8 component can be achieved by simultaneously writing 1s to bits [7:5]. Note 2: Setting bit 8 to a value of 1 requires that bit 0 also be set to a value of 1. See section 6.6.
98
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:14 13:0 Type R R/W Unused. Read all 0's. Value of the Maximum Operational Delay. Table 69 - RX Maximum Operational Delay Register
Data Sheet
0x029A - 0x02A1 (8 reg) 1 register per IMA Group (value in number of cells). For ZL30226 groups 0, 1, 2 and 3 are used. 0000 Description
Address (Hex): Direct access Reset Value (Hex): Bit # 15:9 8:7 6 5:4 Type R R/W R/W R/W
0x02AA (1 reg) Used to initiate an update of the RX Delay registers based on the link and delay value to read. 0000 Description Unused. Read all 0's. Write 00 for normal operation. Writing a 1 will reset the value of the maximum delay over time register for the selected IMA Group (see bits 2:0). Delay register: 11: Maximum Delay over time (see bits 2:0) 10: Current Maximum Delay for an IMA Group (see bits 2:0) 01: Current Minimum Delay for an IMA Group (see bits 2:0) 00: Current Delay for a link (see bits 3:0) Bits 3:0 are used to specify the physical link number. Bits 2:0 are used to specify the physical IMA Group number, based on the delay selected Table 70 - RX Delay Select Register
3:0
R/W
Address (Hex): Direct access Reset Value (Hex): Bit # 15:0 Type R
0x02AD 0000
(1 reg)
Description Each bit reports the recombiner status for a link. A 1 means that the recombiner is enabled. The bit 15 reports for link 15, bit 14 reports for link 14 and so on so forth. Do not write to this register. Table 71 - Enable Recombiner Status Register
99
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:9 8 7:6 Type R R/W R/W Unused. Read all 0's. Reserved. Write 0 for normal operation. Value of M. These 2 bits specifies the value of M for the IMA Group. 00: M = 32 01: M = 64 10: M = 128 11: M = 256 0x0300 - 0x0307 (8 reg) 1 register per TX IMA Group. 00B0 Description
Data Sheet
5 4 3:0
R/W R/W R/W
Timing Mode inserted in ICP cell. A 0 means that the ITC timing mode is inserted in the ICP cell and a 1 means that the CTC timing mode is inserted in the ICP cell. Timing Mode in RoundRobin scheduler. A 0 means that the ITC timing mode is selected and a 1 means that the CTC timing mode is selected for internal operation. Reference Link. These 4 bits define which physical link is to be used as reference for timing purposes. Table 72 - TX Group Control Mode Registers
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 Type R/W
0x0310 - 0x0317 (8 reg) 1 register per 2 links, used in IMA mode only. Link 0 is paired with link 8, link 1 with link 9 and so on. physical link # Description Defines the ICP cell offset of link N+8. The value of M determines which significant bits are used as follows: M = 256; bits 7-0 are used, M = 128; bits 6-0 are used, M = 64; bits 5-0 are used, M = 32; bits 4-0 are used. Defines the ICP cell offset of link N. The value of M determines which significant bits are used as follows: M = 256; bits 7-0 are used, M = 128; bits 6-0 are used, M = 64; bits 5-0 are used, M = 32; bits 4-0 are used. Table 73 - TX ICP Cell Offset Registers
7:0
R/W
100
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15 14 Type R/W R/W
Data Sheet
0x0318 - 0x031F (8 reg) 1 register per 2 links, link 0 is paired with link 8, link 1 with link 9 and so on. The MSByte contains control the link 8-9 and LSByte control links 0-7. 0808 Description Write 1 to count all User cells sent on the TX TDM link N+8. Write 0 to count the total number of cell sent on the TX TDM link N+8. Set to 1 to start sending User Cells in IMA mode on link N+8. Set to 0 to send always Filler and ICP cells in IMA mode
(Note: in non-IMA mode, the control to send User cells is implemented with the UTOPIA Input Link PHY Enable register).
13 12 11 10:8
R/W R/W R/W R/W
Coset value. A 0 will generate HEC with Coset value. When 1, Coset is not added. Cell Scrambling. A 1 enables the scrambling of the cells on the link N+8. Set to 1 for non-IMA mode and clear to 0 for IMA mode. Select the IMA group number BEFORE enabling the IMA mode. Defines IMA group number when the link is configured in IMA mode. Select the IMA group number BEFORE enabling the IMA mode. When configuring the link in non-IMA mode after it was in IMA mode, do not change the IMA group number until the link is reported in non-IMA mode (refer to TX IMA Mode Status Register). Write 1 to count all User cells sent on the TX TDM link N. Write 0 to count the total number of cells sent on the TX TDM link N. Set to 1 to start sending User Cells in IMA mode. Set to 0 to send continuously Filler and ICP cells in IMA mode
(Note: in non-IMA mode, the control to send User cells is implemented with the UTOPIA Input Link PHY Enable register).
7 6
R/W R/W
5 4 3 2:0
R/W R/W R/W R/W
Coset value. A 0 will generate HEC with Coset value, when 1, Coset is not added. Cell Scrambling. A 1 enables the scrambling of the cells on the link N. Set to 1 for non-IMA mode and clear to 0 for IMA mode. Select the IMA group number BEFORE enabling the IMA mode. Defines IMA group number when the link is configured in IMA mode. Select the IMA group number BEFORE enabling the IMA mode. When configuring the link in non-IMA mode after it was in IMA mode, do not change the IMA group number until the link is reported in non-IMA mode (refer to TX IMA Mode Status Register). Table 74 - TX Link Control Registers
Address (Hex): Direct access Reset Value (Hex): Bit # 15 14:11 10:8 Type R/W R/W R/W
0x0321 - 0x0324 (4 reg) 1 register per 2 IMA Group IMA. Group 0 is paired with IMA group 4, IMA group 1 with IMA group 5 and so on. For ZL30226 groups, 0, 1, 2 and 3 are used. 3030 Description 0 for Stuff Indication 1 frame before Stuff event for IMA group N+4. 1 for Stuff Indication 4 frames before stuff event. Overflow limit for IMA group N+4. Default is 6. Underflow limit for IMA group N+4. Default is 1. Table 75 - TX IMA Control Registers
101
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 7 6:3 2:0 Type R/W R/W R/W
Data Sheet
0x0321 - 0x0324 (4 reg) 1 register per 2 IMA Group IMA. Group 0 is paired with IMA group 4, IMA group 1 with IMA group 5 and so on. For ZL30226 groups, 0, 1, 2 and 3 are used. 3030 Description 0 for Stuff Indication 1 frame before Stuff event for IMA group N. 1 for Stuff Indication 4 frames before stuff event. Level overflow limit. Default is 6 for IMA group N. Level underflow limit. Default is 1 for IMA group N. Table 75 - TX IMA Control Registers (continued)
Address (Hex): Direct access Reset Value (Hex): Bit # 15:0 15:10 9:4 3 2:0 Type R W W W R/W
0x0333 (1 write only/read only register). For ZL30226 groups, 0, 1, 2 and 3 are used. The read value is independent from the written value. 0000 Description Reserved Unused Reserved. Write "010000" respectively to bit 9:4 Write 1 with IMA group number in bits 2:0 when adding a link to an existing IMA group. Write 0 when the link is reported in IMA mode. Write IMA group number to which a link is added. Table 76 - TX Add Link Control Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:13 12:8 7:5 4:0 Type R/W R/W R/W R/W
0x0336 - 0x033D (8 reg) 1 register per 2 links, used in IMA mode only. Link 0 is paired with link 8, link 1 is paired with link 9 and so on. physical link # Description Reserved. Write all 0's. Link ID for the link N+8. The value can be between 0 and 31. This is the logical value associated to a physical link. Used in IMA mode only. Reserved. Write all 0's. Link ID for the link N. The value can be between 0 and 31. This is the logical value associated to a physical link. Used in IMA mode only. Table 77 - TX Link ID Registers
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Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:0 Type R 0x0345 (1 reg) 1 register for all links. 0000 Description
Data Sheet
A 1 indicates a specific link (1 link per bit 15:0) is in IMA mode and started by the RoundRobin scheduler. Table 78 - TX Link Active Status Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15 14 ... 1 0 Type R R ... R R
0x0346 (1 reg) 1 register for all links. FFFF Description 1 means Link 15 is not in IMA mode. 1 means Link 14 is not in IMA mode. ... 1 means Link 1 is not in IMA mode. 1 means Link 0 is not in IMA mode. Table 79 - TX IMA Mode Status Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 7 6 ... 1 0 Type R R/W R/W ... R/W R/W
0x0401 (1 reg) 1 register for all groups.For ZL30226 groups, 0, 1, 2 and 3 are used. 0000 Description Unused. Read all 0's. 0: Count total Cells for Group 7. 1: Count only User Cells for Group 7. 0: Count total Cells for Group 6. 1: Count only User Cells for Group 6. ... 0: Count total Cells for Group 1. 1: Count only User Cells for Group1. 0: Count total Cells for Group 0. 1: Count only User Cells for Group 0. Table 80 - Utopia Input Cell Counter Groups Register
103
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15 14 ... 1 0 Type R/W R/W ... R/W R/W 0: Count total Cells for Link 15. 1: Count only User Cells for Link 15. 0: Count total Cells for Link 14. 1: Count only User Cells for Link 14. ... 0: Count total Cells for Link 1. 1: Count only User Cells for Link 1. 0: Count total Cells for Link 0. 1: Count only User Cells for Link 0. Table 81 - UTOPIA Input Cell Counter Links Register 0x0402 (1 reg) 1 register for all links. 0000 Description
Data Sheet
Address (Hex): Direct access Reset Value (Hex): Bit # 15:12 11:8 Type R R/W
0x0403 - 0x0406 (4 regs) 1 register per 2 TX IMA Groups. IMA Group n is paired with IMA group n+4. For ZL30226 groups, 0, 1, 2 and 3 are used. 0C0C Description Unused. Read all 0's. Defines the integration period for IMA Group n+4: 1111: Reserved, do not use 1110: 222 clock cycles ..... 0001: 209 clock cycles 0000: 208 clock cycles Reserved. Defines the integration period for IMA Group n: 1111: Reserved, do not use 1110: 222 clock cycles 1101: 221 clock cycles 1100: 220 clock cycles (preferred value for SHDSL E1 service) 1011: 219 clock cycles (preferred value for SHDSL T1 service) 1010: 218 clock cycles 1001: 217 clock cycles 1000: 216 clock cycles 0111: 215 clock cycles 0110: 214 clock cycles 0101: 213 clock cycles 0100: 212 clock cycles 0011: 211 clock cycles 0010: 210 clock cycles 0001: 209 clock cycles 0000: 208 clock cycles Table 82 - TX IDCR Integration Registers
7:4 3:0
R/W R/W
104
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 7:0 Type R R/W Unused. Read 0's. 0x040B (1 reg) 1 register for all 8 status bits. 0000 Description
Data Sheet
Each bit set to '1' will enable the generation of the interrupt when the corresponding bit in the IRQ IMA Group Overflow Status register is set. There is one bit for each status bit. Table 83 - IRQ IMA Group Overflow Enable Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 7:0 Type R R/W
0x040C (1 reg) 1 register to enable interrupts from IMA Groups. The RxClk signal must be active for correct register operation. 0000 Description Unused. Read all 0's. When set to 1, the corresponding bit in the Overflow Status register can generate an interrupt. A value of 0 inhibits the generation of an interrupt. IMA Groups 7:0.
Table 84 - RX UTOPIA IMA Group FIFO Overflow IRQ Enable Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:4 3 2 1 0 Type R R/W R/W R/W R/W
0x040E (1 reg) 0000 Description Unused. Read all 0's Set when the UTOPIA output clock is missing or too slow. This latched bit is cleared by writing a 0. Set when the UTOPIA input clock is missing or too slow. This latched bit is cleared by writing a 0. Overflow of 1 or more of the TX UTOPIA FIFO. Set when there is no free cell in TX Cell RAM. This latched bit is cleared by writing a 0. Table 85 - General Status Register
Address (Hex): 0x040F (1 reg) Synchronized access Reset Value (Hex): 0080 Bit # 15:12 11 Type R/W R/W Unused. Read all 0's. Reserved. Write 0 for normal operation. Table 86 - Counter Transfer Command Register Description
105
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): 0x040F (1 reg) Synchronized access Reset Value (Hex): 0080 Bit # 10 9:8 Type R/W R/W Description
Data Sheet
Counter values are latched when this bit is changed from 0 to 1 and bit 9:8 are set to 11. Writing 0 has no effect. Write 00 for normal operation without using the latch made. Write 01 to latch the counter value at every rising edge of the signal at LatchClk pin. Write 10 to latch the counter value every 8000 rising edges of the signal at LatchClk pin. Write 11 to latch the counter value every time bit 10 of this register is written to 1. Write: 0 for normal operation. Read: 1 when the transfer is done, 0 when the transfer is pending. Toggle bit. Toggles with every write access to ZL30226/7/8.Write 0 for normal operation. Reserved. Write 0 for normal operation. Read value is undetermined. Reserved. Write 0 for normal operation. Value to write to the Enable bit. 1 to enable, 0 to mask interrupt. This value is transferred when the bit 1:0 are 10. 0 will enable the transfer from the uP to the selected counter. 1 will enable the transfer from the selected counter to the uP. 00: Initialize all the counters with 0. 01: Initiate a read or write of the counter value. 10: Initiate a read or write of the IRQ enable counter bit. 11: Unused. Table 86 - Counter Transfer Command Register (continued)
7 6 5 4 3 2 1:0
R/W R/W R/W R/W R/W R/W R/W
Address (Hex): Direct access Reset Value (Hex): Bit # 15:13 12 11 10 9 8 7 6 Type R R/W R/W R/W R/W R/W R/W R/W
0x0410 - 0x041F (16 reg) 1 register per link. The RxClk and TxClk signals must be active for correct register operation. 0000 Description Unused. Read all 0's. This bit is set when the RX UTOPIA FIFO associated with a Link in non-IMA mode overflows. This bit is cleared by writing 0. This bit is set when the UTOPIA Input counter for all cells (or all Stuff cells event) associated with a link used in non-IMA mode overflows. This bit is cleared by writing 0. This bit is set when the UTOPIA Input counter for Idle Cells associated with a link used in non-IMA mode overflows. This bit is cleared by writing 0. This bit is set when the UTOPIA Input counter for Unassigned Cells associated with a link used in non-IMA mode overflows. This bit is cleared by writing 0. This bit is set when the UTOPIA Input counter for HEC Errored Cells associated with a link used in non-IMA mode overflows. This bit is cleared by writing 0. This bit is set when the TX TDM Link counter for all cells associated with a link overflows. This bit is set when the TX TDM Link counter for Idle or Filler Cells associated with a link overflows. Table 87 - IRQ Link TC Overflow Status Registers
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Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 5 4 3 2 1 0 Type R/W R/W R/W R/W R/W R/W
Data Sheet
0x0410 - 0x041F (16 reg) 1 register per link. The RxClk and TxClk signals must be active for correct register operation. 0000 Description This bit is set when the TX TDM Link counter for TX Stuff Cells associated with a link overflows. This bit is set when the TX TDM Link counter for TX ICP Cells associated with a link overflows. This bit is set when the RX TDM Link counter for all cells (or all Stuff cells event) associated with a link overflows. This bit is set when the RX TDM Link counter for Idle or Filler Cells associated with a link overflows. This bit is set when the RX TDM Link counter for HEC Errored Cells associated with a link overflows. This bit is set when the RX TDM Link counter for bad ICP Cells associated with a link overflows. Table 87 - IRQ Link TC Overflow Status Registers (continued)
Address (Hex): Direct access Reset Value (Hex): Bit # 15:5 4 3 2 1 0 Type R R/W R/W R/W R/W R/W
0x0420 - 0x0427 (8 reg) 1 register per IMA Group. The RxClk and TxClk signals must be active for correct register operation. For ZL30226 groups, 0, 1, 2 and 3 are used. 0000 Description Unused. Read 0's. This bit is set when the RX UTOPIA FIFO associated with an IMA Group overflows. This bit is cleared by writing 0. This bit is set when the counter for all cells associated with an IMA Group overflows. (Input UTOPIA port). This bit is cleared by writing 0. This bit is set when the counter for Idle Cells associated with an IMA Group overflows. (Input UTOPIA port). This bit is cleared by writing 0. This bit is set when the counter for Unassigned Cells associated with an IMA Group overflows. (Input UTOPIA port). This bit is cleared by writing 0. This bit is set when the counter for HEC Errored Cells associated with an IMA Group overflows. (Input UTOPIA port). This bit is cleared by writing 0. Table 88 - IRQ IMA Overflow Status Registers
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Zarlink Semiconductor Inc.
ZL30226/7/8
Data Sheet
Address (Hex): 0x0430 (1 reg) Synchronized access The value in this register is used for internal access to the counter when the transfer command is issued. Reset Value (Hex): 0000 Bit # 15:8 7:0 Type R R/W Unused. Read all 0's. A read accesses the MSB (byte #3) of the Counter selected in the Select Counter register. A write will hold the value to be written to the selected counter. Table 89 - Counter Upper Byte Description
Address (Hex): 0x0431 (1 reg) Synchronized access The value in this register is used for internal access to the counter when the transfer command is issued. Reset Value (Hex): 0000 Bit # 15:0 Type R/W Description A read accesses the byte #2 and byte #1 of the Counter that was selected in the Select Counter register. Byte 2 is in bits 15:8 and byte 1 is in bits 7:0. A write will hold the value to be written to the selected counter. Table 90 - Counter Bytes 2 and 1 Register
Address (Hex): 0x0432 (1 reg) Synchronized access The value in this register is used for internal access to the counter when the transfer command is issued. Reset Value (Hex): 0000 Bit # 15:9 8:5 Type R R/W Unused. Read all 0's. The valid bit combinations are: 1011: UTOPIA Input, counter of all cells for link 1010: UTOPIA Input, counter of Idle cells for link 1001: UTOPIA Input, counter of Unassigned cells for link 1000: UTOPIA Input, counter of cells with HEC error, single or multiple bit errors 0111: TX Link, total number of cells, (or User Cells) 0110: TX Link, number of Idle/Filler cells 0101: TX Link, number of Stuff cells 0100: TX Link, number of ICP cells 0011: RX Link, total number of cells (or stuff cells) 0010: RX Link, number of Idle/Filler cells, (or User Cells) 0001: RX Link, number of cells with HEC errors 0000: RX Link, number of bad ICP cells Other values are not valid and should not be used. Table 91 - Select Counter Register Description
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Zarlink Semiconductor Inc.
ZL30226/7/8
Data Sheet
Address (Hex): 0x0432 (1 reg) Synchronized access The value in this register is used for internal access to the counter when the transfer command is issued. Reset Value (Hex): 0000 Bit # 4:0 Type R/W Description The valid bit combinations are: 10111: IMA Group 7 when UTOPIA Input counter access 10010: IMA Group 6 when UTOPIA Input counter access ... 10001: IMA Group 1 when UTOPIA Input counter access 10000: IMA Group 0 when UTOPIA Input counter access 01111: Link 15 01110: Link 14 ... 00000: Link 0 Other values are not valid and should not be used. Table 91 - Select Counter Register (continued)
Address (Hex): Direct access Reset Value (Hex): Bit # 15:0 Type R/W
0x0433 (1 reg) 1 register for all 16 links. 0000 Description Each bit represents a link. A '1' means that the interrupt form the corresponding link is enabled and that the level of the IRQ pin is low if the corresponding bit in the IRQ Master Register is set. A'0' means that the IRQ level is not affected by the corresponding bit. Table 92 - IRQ Master Enable Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:0 Type R/W
0x0434 (1 reg) 1 register to enable interrupts from the links in TC mode. The RxClk signal must be active for correct register operation. 00 Description When set to 1, any bit set in the IRQ Link TC Overflow Status register can generate an interrupt. A value of 0 inhibits the generation of an interrupt. Each bit corresponds to 1 link. Table 93 - IRQ Link TC Overflow Enable Register
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Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:12 11 10 9 81 Type R R/W R/W R/W R Unused. Read all 0's. A '1' indicates the end of the LODS condition. Cleared by writing a '0'. A '1' indicates the end of the LIF condition. Cleared by writing a '0'. A '1' indicates the end of the LCD condition. Cleared by writing a '0'. 0x0435 - 0x0444 (16 reg) 1 Status register per link. 0000 Description
Data Sheet
A '1' in this bit means that at least one of the IRQ sources from the IMA Group Overflow Status Register is requesting service. This bit can be cleared only by servicing the source of the IRQ. This bit is valid only for the IRQ Link 0 Status register and is reading always a 0 for the IRQ Link 1-15 Status registers. A 1 in this bit means that at least one of the Ready bit used to initiate a transfer of a TX ICP cell for at least 1 of the IMA Group is returned to 1 (meaning that the transfer of the TX ICP cell is complete) or a frame pulse was detected for an IMA Group. This bit is cleared by writing a 0 to it. This bit is valid only for the IRQ Link 0 Status register and is reading always a 0 for the IRQ Link 1-7 Status registers. Overflow in the ICP pre-processing RAM. This status bit can be cleared by writing a '0' to it. ICP Cell with changes received. The link has received an ICP cell which contain one or more changes in it. This status bit can be cleared by writing a '0' to it. IV. The Link has received an ICP cell which contain a violation as defined in Table 16 of IMA Spec. This status bit can be cleared by writing a '0' to it. LODS. The Link is Out of Delay Synchronization. This status bit can be cleared by writing a '0' to it. LIF. Loss of IMA Frame. This status bit can be cleared by writing a '0' to it. LCD Loss of Cell Delineation. This status bit can be cleared by writing a '0' to it. Link Counter Overflow Interrupt. One or more counters associated with the link overflowed. This status bit can be cleared only by reading or writing to the counter(s) which is (are) the source for the IRQ. Table 94 - IRQ Link Status Registers
72
R/W
6 5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R
1. Bit is present only for Link 0. In all other Link Status Registers, this bit is set to 0. 2. Bit is present only for Link 0. In all other Link Status Registers, this bit is set to 0.
Address (Hex): Direct access Reset Value (Hex): Bit # 15:12 11:0 Type R R/W
0x0445 - 0x0454 (16 reg) 1 Enable register per link Status reg. 0000 Description Unused. Read all 0's. Each bit set to '1' will enable the generation of the interrupt when the corresponding bit in the IRQ Link Status register is set. Table 95 - IRQ Link Enable Registers
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Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:0 Type R 0x0455 (1 reg) 1 register for all 16 links. 0000 Description
Data Sheet
Each bit represents a link. A '1' means that the corresponding link has a valid request for interrupt. The level of the IRQ pin is controlled by the bits in this register and the corresponding bits in the IRQ Master Enable Register. A write does not have any affect on the bits in this register. The status bit is not latched and changing the mask bit in the IRQ Master Register has a direct effect on the level of the IRQ pin. Table 96 - IRQ Master Status Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 7:0 Type R R/W
0x0457 (1 reg) 1 register for all IMA groups. 0000 Description Unused. Read all 0's. Each bit set to '1' represent an overflow condition from the IMA Group associated with the bit. There is one bit for each IMA Group. A bit is set when one or more of the 4 counters or the RX UTOPIA FIFO associated with an IMA Group overflows. Table 97 - IRQ IMA Group Overflow Status Register
Address (Hex): Direct access Reset Value (Hex): Address Offset (Hex) 00 01 02 03
8 blocks of 32 words (16 bits) from 0x0500 to 0x05FF Access these locations directly then use transfer command to copy to internal memory. These registers need to be initialized for proper operation. ATM Byte # MSB, LSB 2, 1 4, 3 6, 5 8, 7
Type R/W R/W R/W R/W
Description LSB: Byte 1 (Header 1 byte) of ICP Cell. The value should be set to 0x00 MSB: Byte 2 (Header 2 byte) of ICP Cell. The value should be set to 0x00 LSB: Byte 3 (Header 3 byte) of ICP Cell. The value should be set to 0x00 MSB: Byte 4 (Header 4 byte) of ICP Cell. The value should be set to 0x0B LSB: HEC is always calculated and inserted by the ZL30226/7/8. MSB: OAM, should be set to either 0x01 or 0x03 LSB: Cell ID, Link ID. The bit 7 (Cell ID) is controlled by the ZL30226/7/8, the Link ID is provided by the TX Link ID Register. MSB: IMA Frame Sequence Number. Inserted by the ZL30226/7/8. LSB: ICP Cell Offset. Inserted by the ZL30226/7/8 based on the Link Offset register info. MSB: Link Stuff Indication. Inserted by the ZL30226/7/8 LSB: Status & Control Change Indication. Inserted by the ZL30226/7/8. MSB: IMA ID Table 98 - TX IMA ICP Cell Registers
04
R/W
10, 9
05
R/W
12, 11
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Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Address Offset (Hex) 06 07 08 09- 17 18 19 1A 1B-1F
Data Sheet
8 blocks of 32 words (16 bits) from 0x0500 to 0x05FF Access these locations directly then use transfer command to copy to internal memory. These registers need to be initialized for proper operation. ATM Byte # MSB, LSB 14, 13 16, 15 18, 17 48, 19 50, 49 52, 51 ---, 53 --- ---
Type R/W R/W R/W R/W R/W R/W R/W R/W
Description LSB: Group Status and Control MSB: Synchronization Information, inserted by the ZL30226/7/8 LSB: Tx Test Control MSB: Tx Test Pattern LSB: Rx Test Pattern MSB: Status and Control of links with LID = 0 Status and Control of links with LID in the range 1-30 (Odd numbered byte in LSB and even numbered byte in MSB) LSB: Status and Control of links with LID = 31 MSB: Unused, should be set to 0x6A LSB: End-to-End channel MSB: Upper 2 bits of the CRC-10. Inserted by the ZL30226/7/8 LSB: Lower 8 bits of the CRC-10. Inserted by the ZL30226/7/8 MSB: Not used by ZL30226/7/8. LSB: Not used by ZL30226/7/8. MSB: Not used by ZL30226/7/8.
Table 98 - TX IMA ICP Cell Registers (continued)
Address (Hex): Direct access Reset Value (Hex): Bit # 15 14:10 Type R R/W
0x0600 - 0x060F (16 reg) 1 reg. per TX link. 0000 Description Unused. Read 0. Clock source select These 4 bits are used to select the source for the TXCK for the link when defined as output: The valid combinations are: 00000: RXCK0 00001: RXCK1 00010: RXCK2 00011: RXCK3 00100: RXCK4 00101: RXCK5 00110: RXCK6 00111: RXCK7 01000: RXCK8 01001: RXCK9 01010: RXCK10 01011: RXCK11 01100: RXCK12 01101: RXCK13 01110: RXCK14 01111: RXCK15 10000: REFCK0 10001: REFCK1 10010: REFCK2 10011: REFCK3 Table 99 - TDM TX Link Control Register
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Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 9 Type R/W Clock direction When 0, TXCK is output. When 1, TXCK is input. Remote Loopback When 1, TXCK and DSTo come from the RX pins of the same link. When 0. normal mode. Link enable When 0, the TX port is in high impedance mode When 1, the TX port is active Data rate: Bits 4:3 must be 00 11: 10.0 Mb/sec. (Only links 0, 4, 8 and12 can be used) 10: 5.0 Mb/sec. (Only links 0, 2, 4, 6, 8, 10 and 12 can be used) 01: 2.5 Mb/sec (All links are available) 00: Reserved Reserved: Write 00 for normal operation Reserved: Write 0 for normal operation Clock polarity: When 0, the data is output/sampled at the falling edge of TXCK When 1, the data is output/sampled at the rising edge of TXCK Reserved: Write 1 for normal operation Table 99 - TDM TX Link Control Register (continued) 0x0600 - 0x060F (16 reg) 1 reg. per TX link. 0000 Description
Data Sheet
8
R/W
7
R/W
6:5
R/W
4:3 2 1
R/W R/W R/W
0
R/W
Address (Hex): Direct access Reset Value (Hex): Bit # 15:0 Type R/W
0x0610 - 0x061F (16 reg) Control time slot 15:0. 0000 Description Write all 1's for normal operation. Table 100 - TDM TX Mapping (timeslots 15:0) Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:0 Type R/W
0x0620 - 0x062F (16 reg) Control time slot 31:16. 0000 Description Write all 1's for normal operation. Table 101 - TDM TX Mapping (timeslots 31:16) Register
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Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15 14 ... 1 0 Type R R R R R When 1: TXCK faulty on link 15. When 1: TXCK faulty on link 14. .... When 1: TXCK faulty on link 1. When 1: TXCK faulty on link 0. Table 102 - TXCK Status Register 0x0630 (1 reg) 1 reg. for all 16 TXCK signals. 0000 Description
Data Sheet
Address (Hex): Direct access Reset Value (Hex): Bit # 15 14 ... 1 0 Type R R R R R
0x0631 (1 reg) 1 reg. for all 16 RXCK signals. 0000 Description When 1: RXCK faulty on link 15. When 1: RXCK faulty on link 14. .... When 1: RXCK faulty on link 1. When 1: RXCK faulty on link 0. Table 103 - RXCK Status Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:4 3 2 1 0 Type R R R R R
0x0632 (1 reg) 1 reg. for all 4 REFCK signals. 0000 Description Unused. Read 0's When 1: REFCK3 faulty When 1: REFCK2 faulty When 1: REFCK1 faulty When 1: REFCK0 faulty Table 104 - REFCK Status Register
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Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 15:5 4:0 Type R R/W Unused. Read all 0's. These 5 bits are used to select the source for the signal at PLLREF0: The valid combinations are: 00000: RXCK0 01000: RXCK8 1xxxx: reserved 00001: RXCK1 01001: RXCK9 00010: RXCK2 01010: RXCK10 00011: RXCK3 01011: RXCK11 00100: RXCK4 01100: RXCK12 00101: RXCK5 01101: RXCK13 00110: RXCK6 01110: RXCK14 00111: RXCK7 01111: RXCK15 Table 105 - PLL Reference Control Register 0x0634- 0x0635 (2 reg) 0000 Description
Data Sheet
Address (Hex): Direct access Reset Value (Hex): Bit # 15:12 11 10 9 8 Type R W R/W R/W R/W
0x0700 - 0x070F (16 reg) 1 reg. per RX link. 0000 Description Unused. Read 0's. Reserved. Write 0 for normal operation. Automatic ATM cell synchronization Write 1 for normal operation. Register 0x0741 must also be initialized. Reserved. Write 0 for normal operation. Digital Loopback mode When 1, loopback mode, RXCK and DSTi come from the TX pins of the same link. Both TX and RX blocks operate normally. When 0, normal mode, RXCK and DSTi come from the RX pins of the link Link enable: 0: RX Port is not active 1: RX port is active Data rate: Bits 4:3 must be 00 11: 10.0 Mb/sec. (Only link 0, 4, 8 and 12 can be used) 10: 5.0 Mb/sec. (Only links 0, 2, 4, 6, 8, 10 and12 can be used) 01: 2.5 Mb/sec (All links are available) 00: Reserved Reserved. Write 00 for normal operation. Reserved. Write 0 for normal operation. Clock polarity: When 0, the data is sampled at the rising edge of RXCK When 1, the data is sampled at the falling edge of RXCK Table 106 - TDM RX Link Control Register
7
R/W
6:5
R/W
4:3 2 1
R/W R/W R/W
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Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Bit # 0 Type R/W Reserved. Write 1 for normal operation. Table 106 - TDM RX Link Control Register (continued) 0x0700 - 0x070F (16 reg) 1 reg. per RX link. 0000 Description
Data Sheet
Address (Hex): Direct access Reset Value (Hex): Bit # 15:0 Type R/W
0x0710 - 0x071F (16 reg) Control time slot 15:0. 0000 Description Write all 1's for normal operation. Table 107 - TDM RX Mapping (timeslots 15:0) Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:0 Type R/W
0x0720 - 0x072F (16 reg) Control time slot 31:16. 0000 Description Write all 1's for normal operation. Table 108 - TDM RX Mapping (timeslots 31:16) Register
Address (Hex): Direct access Reset Value (Hex): Bit # 15:8 7:0 Type R R/W
0x0741 (1 reg) 1 reg. for all RX links. 0000 Description Unused. Read 0's. Must write with 54 (0x36). Table 109 - RX Automatic ATM Synchronization Register
116
Zarlink Semiconductor Inc.
ZL30226/7/8
Address (Hex): Direct access Reset Value (Hex): Address Offset (Hex) 00 20 40 60 ... 3A0 3C0 3E0 Type R/W R/W R/W R/W ... R/W R/W R/W Old ICP cell, Link 0. New ICP cell, Link 0. Old ICP cell, Link 1. New ICP cell, Link 1 ... New ICP cell, Link 14 Old ICP cell, Link 15 New ICP cell, Link 15 Table 110 - RX IMA ICP Cell 0x0800 - 0x0BFF, 32 Blocks of 32 words (16-bit wide) Access these locations directly, then use the transfer command to copy to internal memory. unknown Description
Data Sheet
8.0 Application Notes
Traditionally, IMA (Inverse Multiplexing for ATM) is widely adopted in E1/DS1 applications. With the emergence of G.SHDSL (Single-pair High rate Digital Subscribe Line) standards, it is now viable to apply IMA over SHDSL lines. This application note provides a solution of IMA over up to 16 G.SHDSL lines. It serves as a reference design of interfacing ZL30228 to Globespan Virata's Orion chipset. ZL30228 is the second-generation IMA device from Zarlink, which supports IMA over 16 serial bit streams running at a maximum of 2.5 Mbps. It also incorporates a Utopia level 2 bus as ATM interface. The Orion chipset contains a dual-channel DSL framer and two analog front-ends (AFE). It offers a low-power high-density solution for G.SHDSL applications. Connecting ZL30228 and Orion chipset together provides us a complete solution for IMA over G.SHDSL that meets both IMA specification and G.SHDSL specification. The ZL30228 IMA device shown in this reference design can be replaced by ZL30227 (Octal) or ZL30226 (Quad), two IMA devices from the same family. Both ZL30227 and ZL30226 are pin and functional compatible to ZL30228. A block-level diagram is represented in Figure 17.
7.3
Modes of Operation
For ZL30228, the following modes of operation must be selected and programmed: Serial stream mode of up to 2.5 Mb/s per link. TxCK is configured as input. Recommended register settings:
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Zarlink Semiconductor Inc.
ZL30226/7/8
TDM Tx Link Control Register (0x600 - 0x60F) TDM Tx Mapping Registers TDM Tx Mapping Registers (0x610 - 0x61F) (0x620 - 0x62F) should be set to 0x02A3. should be set to 0xFFFF. should be set to 0xFFFF. should be set to 0x04A3. should be set to 0xFFFF. should be set to 0xFFFF.
Data Sheet
TDM Rx Link Control Register (0x700 - 0x70F) TDM Rx Mapping Registers TDM Rx Mapping Registers (0x710 - 0x71F) (0x720 - 0x72F)
Rx Automatic Synchronization Register (0x741) should be set to 0x0036. Orion chipset provides both TxCLK and RxCLK to ZL30228. Orion chipset should be configured in serial interface mode. Zarlink's MSAN - 208 Application Note describes the ZL30226/7/6 to G.SHDSL in detail and also contains the reference design of the interface. For detailed programming of Orion chipset, please refer to Globespan's application notes AN-073.
Link 0 Link 1 UTOPIA Interface Link 2 Link 3
Orion Dual Channel Orion Dual Channel Orion Dual Channel Orion Dual Channel Orion Dual Channel Orion Dual Channel Orion Dual Channel Orion Dual Channel
Link 4 Link 5 Link 6 Link 7
ZL30228
Microport Interface
Link 8 Link 9
Link 10 Link 11 Link 12 Link 13
Link 14 Link 15
Figure 17 - Interface to SHDSL Device
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Zarlink Semiconductor Inc.
ZL30226/7/8
8.0 AC/DC Characteristics
Data Sheet
Absolute Maximum Conditions* Parameter 1 Supply Voltage (2.5 volt core) Supply Voltage (3.3 volt core) Supply Voltage (5.0 volt I/O) Voltage at Digital Inputs (VDD5 connected to 3.3 V) Voltage at Digital Inputs (VDD5 connected to 5.0 V) Current at Digital Inputs Symbol V2.5 V3.3 VDD5 VI3.3 VI5.0 II Min. -0.3 -0.3 -1.0 -1.0 -1.0 -10 Max. 3.1 3.9 6.5 3.9 6.5 10 Units V
2 3
V A C
-40 125 4 Storage Temperature TST * Exceeding these values may cause permanent damage. Functional Operation under these conditions is not implied. Note: Input pins are 5 Volt compatible type.
Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated. Characteristics 1 2 Operating Temperature Supply Voltage Sym. TOP VDD2.5 VDD3.3 VDD5.0 Min. -40 2.38 3.14 4.75 2.5 3.3 5.0 Typ. Max. 85 2.63 3.46 5.25 Units C V Test Conditions
Typical figures are for design aid only.
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Zarlink Semiconductor Inc.
ZL30226/7/8
DC Electrical Characteristics* - Voltages are with respect to ground (Vss) unless otherwise stated Characteristics 1 Supply Current Sym. IDD2.5 IDD3.3 Min. Typ. 300 25/ 29/ 38 2.0 -0.5 35 115 Max. 425 50/ 90/ 156 5.5 0.8 222 V V A Units mA
Data Sheet
Test Conditions System Clock 52 MHz. TDM clock @ 2.5 MHz IDD3.3 Typical for ZL30226/7/8 respectively with ATM traffic, no TDM Ring When VDD5 pins connected to 5.0 VDC
2 3 4
Input High Voltage (Digital Inputs) Input Low Voltage (Digital Inputs) Input Leakage
VIH VIL IILPD IIL
For pins with pull-down resistors and Vin = VSS For all remaining input pins and Vin = VDD3.3 or VSS
-10
1
10 4.6 4.0 pF V mA
5 6 7
Input Pin Capacitance Output High Voltage (Digital Outputs) Output High Current (up_d[15:0], DSTo[15:0], TxCLK[15:0]) Output High Current UTOPIA Output High Current (all other Digital Outputs) Output Low Voltage (Digital Outputs) Output Low Current (up_d[15:0], up_irq, DSTo[15:0], TxCLK[15:0]) Output Low Current UTOPIA Output Low (all others) Output Pin Capacitance High Impedance Leakage (Digital I/O)
CI5V CI VOH IOH 2.4
5 V tolerant inputs All other inputs
VDD -6
Source VOH=2.4 V
8 9 10 11
IOH
-8 -4
mA mA V mA
Source VOH=2.4 V
VOL IOL
VSS 6
0.4
Source VOL=0.4 V
12 13 14 15
IOL
8 4
mA
Source VOL=0.4 V
CO5V CO IOZ -10 1
4.6 4.0 10
pF A
For 5 V tolerant outputs For all other outputs VOH = VSS or VDD
* DC Electrical Characteristics are over recommended temperature and supply voltage. Typical figures are at 25C, typical supply voltages, and for design aid only: not guaranteed and not subject to production testing.
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Zarlink Semiconductor Inc.
ZL30226/7/8
AC Electrical Characteristics - Utopia Interface Transmit Timing ( 50 MHz)1
- Multi-PHY operation with up to 4 input loads of 10 pF each (40 pF total).
Data Sheet
Signal name UTxClk
DIR A->P
Item f1 f1 tT2 tT3 tT4
Description TxClk frequency nominal (8-bit UTOPIA) TxClk frequency nominal (16-bit UTOPIA) TxClk duty cycle TxClk peak-to-peak jitter TxClk rise/fall time Input setup to TxClk Input hold from TxClk Output delay from TxClk Output hold from TxClk Signal going low impedance to TxClk Signal going high impedance to TxCLK Signal going low impedance from TxClk Signal going high impedance from TxClk
Min. 0 0 40% 4 ns 1 ns 1 ns 4 ns 0 ns 1 ns 1 ns
Max. 50 MHz 33 MHz 60% 5% 2 ns 14 ns -
UTxData[15:0], UTxSOC, UTxPAR, UTxEnb, UTxAddr[4:0] UTxClav[0]
A->P
tT5 tT6
A<-P
tOD tT8 tT9 tT10 tT11 tT12
Note 1: Greater than 50 MHz operation is possible with less than worst case duty cycle, jitter and rise/fall times such as 52 MHz operation with 45/55% (or better) duty cycle and 2.5% (or better) jitter.
AC Electrical Characteristics - UTOPIA Interface Receive Timing ( 50 MHz)1
- Multi-PHY operation with up to 4 input loads of 10 pF each (40 pF total).
Signal name URxClk
DIR A->P
Item f1 tT2 tT3 tT4
Description RxClk frequency (nominal) RxClk duty cycle RxClk peak-to-peak jitter RxClk rise/fall time Input setup to RxClk Input hold from RxClk Output delay from RxClk Output hold from RxClk Signal going low impedance to RxClk Signal going high impedance to RxClk Signal going low impedance from RxClk Signal going high impedance from RxClk
Min. 0 40% 4 ns 1 ns 1 ns 4 ns 0 ns 1 ns 1 ns
Max. 50 MHz 60% 5% 2 ns 14 ns -
URxEnb, URxAddr[4:0]
A->P
tT5 tT6
URxData[15:0], URxSOC, URxClav[0], URxPAR2
A<-P
tOD tT8 tT9 tT10 tT11 tT12
Note 1: Greater than 50 MHz operation is possible with less than worst case duty cycle, jitter and rise/fall times such as 52 MHz operation with 45/55% (or better) duty cycle and 2.5% (or better) jitter. Note 2: URxPAR is not valid for cases where URxClk low pulse is shorter than 7.9 nsec.
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Zarlink Semiconductor Inc.
ZL30226/7/8
AC Electrical Characteristics - Utopia Interface Transmit Timing ( 25 MHz) - Multi-PHY operation with up to 8 input loads of 10 pF each (80 pF total) Signal name UTxClk DIR A->P Item f1 tT2 tT3 tT4 UTxData[15:0], UTxSOC, UTxPAR, UTxEnb, UTxAddr[4:0] UTxClav[0] A->P tT5 tT6 A<-P tOD tT8 tT9 tT10 tT11 tT12 Description TxClk frequency (nominal) TxClk duty cycle TxClk peak-to-peak jitter TxClk rise/fall time Input setup to TxClk Input hold from TRxClk Output delay from TxClk Output hold from TxClk Signal going low impedance to TxClk Signal going high impedance to TxClk Signal going low impedance from TxClk Signal going high impedance from TRxClk
Data Sheet
Min. 0 40% 10 ns 1 ns 1 ns 10 ns 0 ns 1 ns 1 ns
Max. 25 MHz 60% 5% 4 ns 27 ns -
AC Electrical Characteristics - UTOPIA Interface Receive Timing ( 25 MHz)
- Multi-PHY operation with up to 8 input loads of 10 pF each (80 pF total).
Signal name URxClk
DIR A->P
Item f1 tT2 tT3 tT4
Description RxClk frequency (nominal) RxClk duty cycle RxClk peak-to-peak jitter RxClk rise/fall time Input setup to RxClk Input hold from RxClk Output delay from RxClk Output hold from RxClk Signal going low impedance to RxClk Signal going high impedance to RxClk Signal going low impedance from RxClk Signal going high impedance from RxClk
Min. 0 40% 10 ns 1 ns 1 ns 10 ns 0 ns 1 ns 1 ns
Max. 25 MHz 60% 5% 4 ns 27 ns -
URxEnb, URxAddr[4:0]
A->P
tT5 tT6
URxData[15:0], URxSOC, URxClav[0], URxPAR
A<-P
tOD tT8 tT9 tT10 tT11 tT12
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Zarlink Semiconductor Inc.
ZL30226/7/8
Data Sheet
Clock
Signal tT5, tT7 Input Setup To Clock tT6, tT8 Input Hold From Clock
Figure 18 - Setup and Hold Time Definition
Clock Signal Valid tT91 Signal tT11 Signal Going Low Impedance From Clock tT12 Signal Going High Impedance From Clock Signal Going High Impedance tT101
Figure 19 - Tri-State Timing
tclk_min
Clock
tIS1 Signal tOD Signal Valid
Figure 20 - Output Delay Timing Note 1: The UTOPIA specification AC Characteristics are based on the timing specification for the receiver side of a signal. In the case where the ZL30226/7/8 is driving a signal (sending side), the input setup to the (next) clock can be derived using the worst case period of the actual clock used. tIS would be equivalent to tT5 or tT7 for the device that receives the output from the ZL30226/7/8. tIS = tclk_min - tOD
123
Zarlink Semiconductor Inc.
ZL30226/7/8
AC Electrical Characteristics - External Memory Interface Timing - Read Access Item Description ZL30226/7/8 System Clock Period tRC tAVRS tAVRH tCSRS tCSRH tWERS tWERH tRDS tRDH Read Cycle Time Address Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Enable* Setup Time Write Enable* Hold Time Data Setup Time Data Hold Time Min. 19 ns 10 ns1 Typ. 20 ns
Data Sheet
.
Max
0 ns 0 ns 1 ns 1 ns 0 ns 0 ns 1.5 ns 1 ns
9.5 ns
7.5 ns
9.5 ns
0
Typical figures are at 25C, VDD=3.3 V, and for design aid only: not guaranteed and not subject to production testing. Note 1: tRC = tCLK - tCSRS - tRDS.
tclk
System Clock
tavrh
tavrs
SR_A[18:0]
Address Valid
trc
SR_CS
tcsrs
tcsrh twerh
SR_WE
twers trdh
SR_D[7:0]
Data Valid
trds
Figure 21 - External Memory Interface Timing - Read Cycle
124
Zarlink Semiconductor Inc.
ZL30226/7/8
AC Electrical Characteristics - External Memory Interface Timing - Write Access Item tCLK tWC tAVWS tAVWH tCSWS tCSWH tWEWS tWEWH tWDS tWDH Description ZL30226/7/8 System Clock Period Write Cycle Time Address Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Enable* Setup Time Write Enable* Hold Time Data Setup Time Data Hold Time 0 ns Min. 19 ns 12.5 ns1 Typ. 20 ns
Data Sheet
Max.
0 ns 0 ns 1 ns 1 ns 0 ns 0 ns
9.5 ns
7.5 ns 7.5 ns 9.5 ns
19 ns
Typical figures are at 25C, VDD=3.3 V, and for design aid only: not guaranteed and not subject to production testing. Note 1: tWC = tCLK - tCSWS.
tclk
System Clock
tavwh
tavws
SR_A[18:0]
Address Valid
twc
SR_CS
tcsws
tcswh twewh
SR_WE
twews twds twdh
SR_D[7:0]
Data Valid
Note: The SR_WE signal stays LOW until a READ cycle is to be performed Refer to SRAM Control Register to select the number of cycles
Figure 22 - External Memory Interface Timing - Write Cycle
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8.1 CPU Interface Timing
Data Sheet
The CPU Interface of the ZL30226/7/8 supports both the Motorola and Intel timing modes. No Mode Select pin is required. With Motorola devices, the Motorola R/W-signal is connected to the UP_R/W pin and the UP_OE pin is tied to ground. There is no DS signal and the UP_CS signal is taken to access the ZL20226/227/228. When used with Intel devices, the READ-signal is connected to the UP_OE pin and the WRITE-signal is connected to the UP_R/W pin. When performing a read operation, data is placed on the bus immediately after UP_CS is lLOW and UP_R/W is HIGH for the Motorola timing mode and after the UP_CS and UP_OE signals are LOW for Intel timing. When performing a write operation in Motorola timing mode, the data is clocked into an ZL30226/7/8 pre-load register upon the first rising edge of UP_R/W or UP_CS signals. In Intel timing mode, the data is clocked into ZL30226/7/8 pre-load register upon the first rising edge of UP_R/W or UP_CS signals. Right after that transition, the data is transferred to the ZL30226/7/8's internal register. Writing data into this register can take up 2 system clock cycles.
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AC Electrical Characteristics - CPU Interface Motorola Timing - Read Cycle Characteristics 1 2 3 4 5 R/W set-up time to UP_CS falling edge Data valid after UP_CS falling edge. UP_AD or UP_R/W hold time after UP_CS rising edge Data hold time after rising edge of UP_CS UP_D low impedance after falling edge of UP_CS Sym. tWS tACC tAH tCH tLI 4 2 2 20 Min. 1 35 Typ. Max. Units ns ns ns ns ns
Data Sheet
Test Conditions
150 pf loads
150 pf loads
UP_OE
(low)
UP_CS tws UP_R/W tah UP_AD[11:0] tli UP_D[15:0] tacc Data Valid tch Address Valid
Figure 23 - CPU Interface Motorola Timing - Read Access
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AC Electrical Characteristics - CPU Interface Intel Timing - Read Cycle Characteristics 1 2 3 4 5 R/W set-up time to UP_CS falling edge Data valid after both UP_OE and UP_CS are low. UP_AD or UP_R/W hold time after UP_OE rising edge Data hold time after the first rising edge of UP_CS or UP_OE UP_D low impedance after falling edge of UP_OE Sym. tWS tACC tAH tCH tLI 4 2 2 20 Min. 1 35 Typ. Max. Units ns ns ns ns ns
Data Sheet
Test Conditions
150 pf loads
150 pf loads
UP_OE
UP_CS tws UP_R/W tah UP_AD[11:0] tli UP_D[15:0] tacc Data Valid tch Address Valid
Figure 24 - CPU Interface Intel Timing - Read Access
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AC Electrical Characteristics - CPU Interface Motorola Timing - Write Cycle Characteristics 1 2 3 4 5 UP_R/W set-up time to UP_CS falling edge Address and Data set up before rising edge of UP_CS UP_AD and Data hold time after UP_CS rising edge UP_R/W low after rising edge or UP_CS UP_CS high before next UP_CS low Sym. tWS tSU tADH tWH tCSH Min. 1 10 4 1 2 (see Note 1) Typ. Max. Units ns ns ns ns cycle system clock
Data Sheet
Test Conditions
Note 1 - For internal synchronization purposes, 2 system clock cycles are required between a write access and the next valid access.
UP_OE
UP_CS
tws
UP_R/W
twh tadh
tcsh
UP_AD[11:0]
Address Valid
UP_D[15:0]
Data Valid
tsu Figure 25 - CPU Interface Motorola Timing - Write Access
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AC Electrical Characteristics - CPU Interface Intel Timing - Write Cycle Characteristics 1 2 3 4 5 UP_CS set-up time to UP_R/W falling edge Address and Data set up before rising edge of UP_R/W UP_AD, UP_CS and Data hold time after UP_R/W rising edge UP_R/W low after rising edge or UP_CS UP_CS high before next UP_CS low Sym. tWS tSU tADH tCSH tWH Min. 1 10 4 1 2 (see Note 1) Typ. Max. Units ns ns ns ns cycle system clock
Data Sheet
Test Conditions
Note 1 - For internal synchronization purposes, 2 system clock cycles are required between a write access and the next valid access.
UP_OE (READ) tcsh UP_CS tws UP_R/W (WRITE) twh
tadh ADDRESS VALID tsu
UP_A[11:0]
UP_D[15:0]
DATA VALID
Figure 26 - CPU Interface Intel Timing - Write Access
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AC Electrical Characteristics - Serial Streams CLK Characteristic 1 2 3 CLK Period Bit rate up tp10.0 Mb/s CLK Pulse Width High Bit rate up tp10.0 Mb/s CLK Pulse Width Low Bit rate up tp10.0 Mb/s Clock Rise/Fall Time Sym. tCP 90 tCH 45 tCL 45 tr, tf 50 10 ns ns 50 ns 100 ns Min. Typ. Max. Units
Data Sheet
Notes
4
AC Electrical Characteristics - Serial Streams Characteristic 1 2 3 4 5 6 Sti Set-up Time Sti Hold Time Sto Delay - Active to Active STo delay - Active to High-Z STo delay - High-Z to Active Output Driver Enable (ODE) Delay Sym. tSIS tSIH tSOD tDZ tZD tODE Min. 5 10 25 25 25 25 ns Typ. Max. Units ns ns ns Test Conditions
CL=150 pF CL=150 pF CL=150 pF CL=150 pF
tCH CLK (positive) CLK (negative) tSIS STi Bit 0 tSIH Bit 6
tCP VIH(min) VCT VIL(max)
tr
tCL
tf
VCT
Bit 5
VCT
tSOD STo Bit 0 Bit 7 Bit 6 Bit 5 VCT
Figure 27 - Serial TDM Bus Timing
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AC Electrical Characteristics - TDM Ring Bus Characteristic 1 2 3 4 5 6 TXRingClk/RXRingClk period TXRingClk/RXRingClk period high TXRingClk/RXRingClk period low TXRingSync/TXRingData output delay RxRingSync/RXRingData setup time RxRingSync/RxRingData hold time Sym. tRTxP/tRRxP tRTxH/tRRxH tRTxL/tRRxL tRTxOD tRRxS tRRXH 0 2 2 Min. 19 Typ. 20 10 10 4 Max. 20 Units ns ns ns ns ns ns
Data Sheet
Test Conditions Must be synchronous with the System Clock
Typical figures are at 25C, VDD=3.3 V, and for design aid only: not guaranteed and not subject to production testing.
tRTxH TXRingClk tRTxL TXRingSync tRTxOD TXRingData [7:0]
tRTxP
Figure 28 - TDM Ring TX Timing Diagram
tRRxH tRRxP RXRingClk tRRxS RXRingSync tRRxL
tRRxH RXRingData [7:0]
Figure 29 - TDM Ring RX Timing Diagram
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AC Electrical Characteristics - JTAG Port and RESET Pin Timing Parameter TCK period width TCK period width LOW TCK period width HIGH TDI setup time to TCK rising TDI hold time after TCK rising TMS setup time to TCK rising TMS hold time after TCK rising TDO delay from TCK falling TRST pulse width Symbol tTCLK tTCLKL tTCLKH tDISU tDIH tMSSU tMSH tDOD tTRST 15 Min. 100 40 40 2 33 2 5 20 Typ. Max. Units ns ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions BSDL spec's 12 MHz
CL = 30 pF
RESET pulse width tRST 2 ms 70 Typical figures are at 25C, VDD=3.3 V, and for design aid only: not guaranteed and not subject to production testing.
MCLK cycles
tmssu tmsh
TMS
tdih tdisu
TDI
ttclk ttclkh ttclkl
TCK
tdod
TDO
ttrst
TRST
Figure 30 - JTAG Port Timing
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AC Electrical Characteristics - System Clock and Reset Parameter CLK period width 1 Symbol tCLK Min. 19 Typ. 20 Max. 20 Units ns
Data Sheet
Test Conditions For full operation of TDM Ring, otherwise could be longer The min CLK period width restrictions still need to be maintained The minimum time is measured at 1.4V Between 10%-90% of voltage levels Between 10%-90% of voltage levels
CLK period width LOW
tCLKL
8.5
10
ns
CLK period width HIGH CLK rising CLK falling RESET pulse width
tCLKH tCLKR tCLKF tRST
8.5
10 6 6
ns ns ns clk period
10
Note 1: The System Clock period cannot be longer than the TX or RX Utopia clock period. Typical figures are at 25C, typical supply voltages, and for design aid only: not guaranteed and not subject to production testing.
tclk
CLK
tclkr
tclkf
tclkh
tclkl
RESET
trst
Figure 31 - System Clock and Reset
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9.0
AAL ATM CBR CDV CPE CRC CTC DSU FE GSM GTSM HEC IDCR I/F IFSM IMA ISDN ITC LCD LID LIF LODS LOF LOS LSM M MIB MVIP NE OAM OCD OIF PDH PHY PMD
Data Sheet
List of Abbreviations and Acronyms
ATM Adaptation Layer Asynchronous Transfer Mode Constant Bit Rate Cell Delay Variation Customer Premises Equipment Cyclic Redundancy Check Common Transmit Clock Data Service Unit Far End Group State Machine Group Transmit State Machine Header Error Control IMA Data Cell Rate Interface Ima Frame State Machine Inverse Multiplexing for ATM Integrated Services Digital Network Independent Transmit Clock Loss of Cell Delineation Link Identification Loss of IMA Frame Link Out of Delay Synchronization Loss Of Frame Loss of Signal Link State Machines IMA Frame Size Management Information Base Multi-Vendor Integration Protocol Near End Operations, Administration and Maintenance Out of Cell Delineation (anomaly) Out of IMA Frame (anomaly) Plesiochronous Digital Hierarchy Physical Layer Physical Medium Dependent
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QoS RAI RDI RFI SAR SCCI SOC TC TRL TRLCR UTOPIA UNI Quality of Service Remote Alarm Indication Remote Defect Indication Remote Failure Indication Segmentation and Reassembly Status and Control Change Indication Start of Cell Transmission Convergence Timing Reference Link Timing Reference Link Cell Rate Universal Test and Operations Physical Interface for ATM User Network Interface
Data Sheet
10.0
ATM Glossary
Asynchronous Transfer Mode Adaptation Layer (AAL) - Standardized protocols used to translate higher layer services from multiple applications into the size and format of an ATM cell. Individual protocols are indexed as per the examples below: AAL0 - Native ATM cell transmission proprietary protocol featuring 5-byte header and 48-byte user payload. AAL1 - Used for the transport of constant bit rate, time-dependent traffic (e.g., voice, video); requires transfer of timing information between source and destination; maximum of 47-bytes of user data permitted in payload as an additional header byte is required to provide sequencing information. AAL5 - Usually used for the transport of variable bit rate, delay-tolerant data traffic and signalling which requires little sequencing or error-detection support. Active - This is a link state indicating the link is capable of passing ATM Layer cells in the specified direction. Aligned - IMA Frames are said to be aligned if they are transmitted simultaneously. Asynchronous 1. Not synchronous; not periodic. 2. The temporal property of being sourced from independent timing references, having different frequencies and no fixed phase relationship 3. In telecommunications, data which is not synchronized to the public network clock. 4. The condition or state of being unable to determine exactly when an event will transpire prior to its occurrence. Asynchronous Transfer Mode (ATM) - A method of organizing information to be transferred into fixed-length cells; asynchronous in the sense that the recurrence of cells containing information from an individual user is not necessarily periodic.
Note: Although ATM cells are transmitted synchronously to maintain the clock between sender and receiver, the sender transmits data cells on an as available basis and transmits empty cells when idle. The sender is not limited to transmitting data every Nth cell.
Blocked - The Blocked State is a Group State indicating that the Group has been inhibited. Blocking - Blocking is a transitional state that allows graceful transition into the Unusable State without loss of ATM layer cells.
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Data Sheet
Cell - Fixed-size information package consisting of 53 bytes (octets) of data; of these, 5 bytes represent the cell header and 48 bytes carry the user payload and required overhead. Cell Delay Variation (CDV) - a QoS parameter that measures the peak-to-peak cell delay through the network; results from buffering and cell scheduling. Common Transmit Clock (CTC) Configuration - This is a configuration where the transmit clocks of all links within the IMA group are derived from the same clock source. Constant Bit Rate - An ATM service category supporting a constant or guaranteed rate, with timing control and strict performance parameters. Used for services such as voice, video, or circuit emulation. Filler Cell - A Filler Cell is used to fill in the IMA frame when no cells are available at the ATM layer. It is used for performing cell rate decoupling at the IMA sublayer (e.g., similar to the Idle Cell used in single link interfaces). Header Error Control (HEC) - ATM equipment (usually the PHY) uses the fifth octet in the ATM cell header to check for an error and correct the contents of the header; CRC algorithm allows for single-error correction and multiple-error detection. I.363 - ITU-T Recommendation specifying the AALs for B-ISDN. IMA Frame - The IMA Frame is used as the unit of control in the IMA protocol. It is defined as M consecutive cells, on each of N links, where 1 N 32 (determined by the UM and IMA link start-up procedure), in an IMA Group. One of the M cells on each of the N links is an ICP cell that occurs within the frame at the ICP cell offset position. This offset position may be different between links. The IMA Frame is Aligned on all links. Differential link delay can cause the reception to be `mis-aligned` in time. Alignment can be recovered using a link delay synchronization mechanism. The ICP `Stuff` mechanism is a controlled violation of the IMA consecutive frame definition. IMA Group - The IMA Group is a `group` of links at one end of a 'circuit' that establish an IMA virtual link to another end. IMA Sublayer - The IMA Sublayer is part of the Physical Layer that is located between the interface specific Transmission Convergence Sublayer and the ATM Layer. IMA Virtual Link - The IMA Virtual Link is a virtual circuit established between two IMA ends over a number of Physical Links (i.e., IMA Group). Inhibiting - Inhibiting is a voluntary action that disables the capacity of a group or link to carry ATM Layer cells for reasons other than reported problems. Insufficient Links - This is a Group State indicating that the group does not have sufficient links to be in the Operational State. Independent Transmit Clock (ITC) Configuration - This is a configuration where the transmit clock of at least one link within the IMA Group is not derived from a common clock source. Isochronous - The temporal property of an event or signal recurring at known periodic time intervals (e.g., 125 s). Isochronous signals are dependent on some uniform timing, or carry their own timing information embedded as part of the signal. Examples are DS-1/T1 and E1. From the root words, "iso" meaning equal, and "chronous" meaning time. ITU-T - International Telecommunications Union Telecommunications Standards Sector. Layer Management Functions - The Layer Management Functions relate to processing of actions such as configuration, fault monitoring and performance monitoring within the group.
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Data Sheet
Loss of Cell Delineation (LCD) - The LCD defect is reported when the OCD anomaly persists for the period of time specified in ITU-T Recommendation I.432(30). The LCD defect is cleared when the OCD anomaly has not been detected for the period of time specified in ITU-T Recommendation I.432. LCD Remote Failure Indication (LCD-RFI) - The LCD-RFI is reported to the FE when a link defect is locally detected. The LCD-RFI defect is not always required on the link interface. Link Delay Synchronization (LDS) - The LDS is an event indicating that the link is synchronized with the other links within the IMA Group with respect to differential delay. Loss of IMA Frame (LIF) Defect - the LIF defect is the occurrence of persistent OIF anomalies for at least Gamma + 2 IMA Frames. Link Out of Delay (LODS) Synchronization Defect - The LODS is a link event indicating that the link is not synchronized with the other links within the IMA Group. Multi-Vendor Integration Protocol (MVIP) - MVIP standards are designed to support the inter-operability of products from different manufacturers and the portability of computer software between products from different manufacturers with the goal of facilitating new and improved applications of computer and communications equipment. Out of Cell Delineation (OCD) Anomaly - As specified in ITU-T Recommendation I.432(30), an OCD anomaly is reported when ALPHA consecutive cells with incorrect HEC are received. It ceases to be reported when DELTA consecutive cells with correct HEC are received. Out of IMA Frame (OIF) Anomaly - The OIF is the occurrence of an IMA anomaly as defined in the Inverse Multiplexing for ATM Specification. Operational - The Operational State is a group state that has sufficient links in both the transmit and receive directions to carry ATM Layer cells. Plesiochronous - The temporal property of being arbitrarily close in frequency to some defined precision. Plesiochronous signals occur at nominally the same rate, any variation in rate being constrained within specific limits. Since they are not identical, over the long term they will be skewed from each other. This will force a switch to occasionally repeat or delete data in order to handle buffer under-flow or overflow. (In telecommunications, this is known as a frame slip). Physical Layer (PHY) - Bottom layer of the ATM Reference Model; provides ATM cell transmission over the physical interfaces that interconnect the various ATM devices. Quality of Service (QoS) - ATM performance parameters that characterize the transmission quality over a given VC (e.g cell delay variation; cell transfer delay, cell loss ratio). Stuff Event - The Stuff Event is the repetition of an ICP Cell over one IMA Link to compensate for a timing difference with other links within the IMA Group. Synchronous 1. The temporal property of being sourced from the same timing reference. Synchronous signals have the same frequency, and a fixed (often implied to be zero) phase offset. 2. A mode of transmission in which the sending and receiving terminal equipment are operating continually at the same rate and are maintained in a desired phase relationship by an appropriate means.
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Data Sheet
Universal Test and Operations Physical Interface for ATM (UTOPIA) - A PHY-level interface to provide connectivity between ATM components. Unusable - The Unusable State is a link state indicating that a link is not in use due to a fault, inhibition, etc. Usable - The Usable State is a link state indicating the link is ready to operate in the specified direction, but is waiting to move to the Action State. Virtual Channel (VC) - One of several logical connections defined within a virtual path (VP) between two ATM devices; provides sequential, unidirectional transport of ATM cells. Also Virtual Circuit. Glossary References: The ATM Glossary - ATM Year 97 - Version 2.1, March 1997 The ATM Forum Glossary - May 1997 ATM and Networking Glossary (http://www.techguide.com/comm/index.html) Zarlink Semiconductor Glossary of Telecommunications Terms - May 1995.
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c Zarlink Semiconductor 2003 All rights reserved.
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